central-arch-doc

Author	SHA1	Message	Date
Elyan	955251bea6	Split the instructions in multiple files and added move and branch instructions All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 17s Details	2024-11-02 00:44:24 +01:00
Elyan	3459319b1a	Added info on the hardware debug logging output register in ss3 All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 16s Details	2024-11-01 16:06:08 +01:00
Elyan	32d34b9283	Added details for subsystem register sr0: Simulation Control All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 20s Details	2024-10-31 15:09:49 +01:00
Elyan	5f44805554	Added info on esr registers and reset behavior All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 15s Details	2024-10-31 10:12:53 +01:00
Elyan	ab401b9d1b	Added ssr/ssw instructions and added subsystems information All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 15s Details	2024-10-31 00:53:06 +01:00
Elyan	c0f7b6484c	Added conditions and registers encodings in instruction formats All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 15s Details	2024-10-29 23:08:23 +01:00
Elyan	bdf98a7f7d	Added psr and esr special registers All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 17s Details	2024-10-26 15:43:41 +02:00
Elyan	08ea4f8d07	Added the other LDR variants and the SVC instruction, updated layout All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 14s Details	2024-10-23 00:02:49 +02:00
Elyan	ee660d0798	Only 4 levels are numbered All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 13s Details	2024-10-21 23:30:19 +02:00
Elyan	ca71abdc10	Added the LDRIRW variant of the LDR instruction All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 14s Details	2024-10-21 23:19:31 +02:00
Elyan	07acc7ff1e	Started to document instructions and updated encoding formats (colors + added conditions) All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 13s Details	2024-10-20 23:09:13 +02:00
Elyan	f3bf60db75	Fix typo and reformulate phrases	2024-10-20 18:23:00 +02:00
Elyan	ea9b0f181f	Added info about subsystems and channel I/O, enhanced layout and reformulated phrases. All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 12s Details	2024-10-19 19:03:38 +02:00
Elyan	58f56360e7	Created a proper intro and refactored the doc All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 11s Details	2024-10-15 00:14:23 +02:00
Elyan	9615379f80	Added EE modes and registers + enhanced layout All checks were successful Central(Architecture) Docs Build / Build Documentation (push) Successful in 10s Details	2024-10-13 23:41:09 +02:00
Elyan	8f2ee738da	Added Wavedrom register diagrams for the instruction encoding formats	2024-10-13 01:27:08 +02:00
Elyan	2bcab589b8	Added info on the data handled by the CPU	2024-10-13 00:47:10 +02:00
Elyan	234a92d5e0	Initial commit	2024-10-12 23:18:36 +02:00

18 Commits