Added the LDRIRW variant of the LDR instruction
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Elyan 2024-10-21 23:19:31 +02:00
parent 07acc7ff1e
commit ca71abdc10

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@ -147,8 +147,19 @@ Assembler syntax::
+
[source]
----
ldr{cond} dst, [src, off]
ldr<cond?> <dst>, [<src>, <off?>]
----
+
Where:
[horizontal]
cond::: Optional condition.
dst::: Destination register.
src::: Source register.
off:::
Optional offset immediate.
Must be a multiple of 4 and in the range 0-8188.
If omitted, then 0 is used.
Examples::
+
[source]
@ -160,6 +171,50 @@ ldr.eq r5, [r4] ; If the last comparison resulted in an 'eq' condition status
; then reads a word from the memory address in r4 into r5.
; Else, does nothing.
----
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
[horizontal]
MemFault:::
If the memory address being accessed is invalid, non readable or not paged in.
The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place.
====== LDRIRW: Load Register Immediate Pre-indexed with Write-back
Description::
Increments the source register then reads a word from memory into the destination register.
The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register.
Encoding:: A-Type
Assembler syntax::
+
[source]
----
ldr<cond?> <dst>, ![<src>, <off?>]
----
+
Where:
[horizontal]
cond::: Optional condition.
dst::: Destination register.
src::: Source register.
off:::
Optional offset immediate.
Must be a multiple of 4 and in the range 0-8188.
If omitted, then 4 is used.
Examples::
+
[source]
----
ldr r1, ![r0] ; Increments r0 by 4 then reads a word from the memory address
; in r0 into r1.
ldr r3, ![r2, 8] ; Increments r2 by 8 then reads a word from the memory address
; in r2 into r3.
ldr.eq r5, ![r4] ; If the last comparison resulted in an 'eq' condition status,
; then increments r4 by 4 and reads a word from the memory
; address in r4 into r5. Else, does nothing.
----
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::