Added the LDRIRW variant of the LDR instruction
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@ -147,8 +147,19 @@ Assembler syntax::
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+
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[source]
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----
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ldr{cond} dst, [src, off]
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ldr<cond?> <dst>, [<src>, <off?>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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dst::: Destination register.
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src::: Source register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range 0-8188.
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If omitted, then 0 is used.
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Examples::
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[source]
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@ -160,6 +171,50 @@ ldr.eq r5, [r4] ; If the last comparison resulted in an 'eq' condition status
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; then reads a word from the memory address in r4 into r5.
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; Else, does nothing.
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----
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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[horizontal]
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MemFault:::
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If the memory address being accessed is invalid, non readable or not paged in.
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The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place.
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====== LDRIRW: Load Register Immediate Pre-indexed with Write-back
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Description::
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Increments the source register then reads a word from memory into the destination register.
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The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register.
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Encoding:: A-Type
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Assembler syntax::
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+
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[source]
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----
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ldr<cond?> <dst>, ![<src>, <off?>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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dst::: Destination register.
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src::: Source register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range 0-8188.
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If omitted, then 4 is used.
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Examples::
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+
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[source]
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----
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ldr r1, ![r0] ; Increments r0 by 4 then reads a word from the memory address
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; in r0 into r1.
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ldr r3, ![r2, 8] ; Increments r2 by 8 then reads a word from the memory address
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; in r2 into r3.
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ldr.eq r5, ![r4] ; If the last comparison resulted in an 'eq' condition status,
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; then increments r4 by 4 and reads a word from the memory
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; address in r4 into r5. Else, does nothing.
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----
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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