Added ssr/ssw instructions and added subsystems information
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@ -11,3 +11,4 @@ include::execution-engine-spec/intro.adoc[]
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include::execution-engine-spec/program-and-exception-status-registers.adoc[]
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include::execution-engine-spec/channel-io-overview.adoc[]
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include::execution-engine-spec/instructions.adoc[]
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include::execution-engine-spec/subsystems.adoc[]
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@ -192,3 +192,54 @@
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|sp_fault
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|===
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[id=subsystems-encoding]
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==== Subsystems Encoding
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[%header,cols="^1,^1,2"]
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|===
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2+|Value
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|Name
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|0000~2~
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|0000~16~
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|ss0
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|0001~2~
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|0001~16~
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|ss1
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|0010~2~ .. 1110~2~
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|0002~16~ .. 000e~16~
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|ss2 .. ss14
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|1111~2~
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|000f~16~
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|ss15
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|===
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[id=subsystems-registers-encoding]
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==== Subsystems Registers Encoding
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[%header,cols="^1,^1,2"]
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|===
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2+|Value
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|Name
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|00000000~2~
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|00000000~16~
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|sr0
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|00000001~2~
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|00000001~16~
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|sr1
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|00000010~2~ .. 11111110~2~
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|00000002~16~ .. 000000fe~16~
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|sr2 .. sr254
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|11111111~2~
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|000000ff~16~
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|sr255
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|===
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@ -23,21 +23,25 @@ rs1::
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rs2::
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Source register 2.
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imm::
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Immediate value.
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Immediate value. +
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Can be interpreted as signed or unsigned depending on the instruction.
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reg::
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Source/destination register on the _Execution Engine_ side.
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Source/destination register on the _Execution Engine_ side. +
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See <<registers-encoding>>.
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sid::
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Subsystem ID.
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Subsystem ID. +
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See <<subsystems-encoding>>.
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sre::
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Source/destination register on the subsystem side.
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Source/destination register on the subsystem side. +
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See <<subsystems-registers-encoding>>.
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cmd::
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Subsystem command.
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Subsystem register command. +
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Specific to the accessed subsystem register. More info in <<subsystems>>.
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include::instructions-operands-encoding.adoc[]
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<<<
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=== Instruction list
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=== Instruction List
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#TODO: List instructions#
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* NOP instruction
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@ -50,7 +54,7 @@ include::instructions-operands-encoding.adoc[]
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* system mode instructions (svc, uret, sret, ...)
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* subsystems instructions (ssr & ssw)
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==== Miscellaneous instructions
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==== Miscellaneous Instructions
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===== NOP: No Operation
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[wavedrom, ,svg]
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....
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@ -78,7 +82,7 @@ Exceptions:: None.
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x7f, type: 8, attr: '0x7f'},
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{bits: 7, name: 0x7f, type: 8, attr: '0x7e'},
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{bits: 25, name: 'svc_num', type: 5}
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], config: {label: {right: 'SVC'}}}
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....
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@ -97,7 +101,7 @@ Where:
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[horizontal]
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svc_num:::
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A constant identifying the privileged operation to execute. +
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Must be in the range 0-33554431 (0x0-0x1FFFFFF).
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Must be in the range 0..33554431 (0x0..0x1FFFFFF).
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Examples::
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+
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@ -439,3 +443,101 @@ Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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==== Subsystems Instructions
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===== SSR: Subsystem Register Read
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x7d, type: 8, attr: '0x7d'},
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{bits: 5, name: 'reg', type: 2},
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{bits: 4, name: 'sid', type: 7},
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{bits: 8, name: 'sre', type: 2},
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{bits: 8, name: 'cmd', type: 8}
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], config: {label: {right: 'SSR'}}}
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....
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Description::
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Reads a value from a subsystem register into an _Execution Engine_ register.
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Encoding:: E-Type
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Assembler syntax::
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+
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[source]
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----
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ssr <sid>, <reg>, <sre>, <cmd>
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----
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+
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Where:
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[horizontal]
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sid:::
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The subsystem identifier.
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Should be in the range *ss0*..*ss15*.
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reg::: The _Execution Engine_ destination register.
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sre:::
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The subsystem source register.
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Should be in the range *sr0*..*sr255*.
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cmd::: The subsystem register specific command to use for reading.
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Examples::
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+
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[source]
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----
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ssr ss0, r1, sr0, 1 <1>
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ssr ss15, pc, sr32, 0 <2>
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----
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<1> Reads the *sr0* register from the *ss0* subsystem into *r1* using the command _0x1_ to do so.
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<2> Reads the *sr32* register from the *ss15* subsystem into *pc* using the command _0x0_ to do so.
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Privileged instruction:: No. (The access control is done at the register/command level).
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Updates program state flags:: No.
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Exceptions:: UnknownInstr.
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<<<
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===== SSW: Subsystem Register Write
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x7e, type: 8, attr: '0x7e'},
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{bits: 5, name: 'reg', type: 2},
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{bits: 4, name: 'sid', type: 7},
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{bits: 8, name: 'sre', type: 2},
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{bits: 8, name: 'cmd', type: 8}
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], config: {label: {right: 'SSW'}}}
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....
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Description::
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Writes a value from an _Execution Engine_ register into a subsystem register.
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Encoding:: E-Type
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Assembler syntax::
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+
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[source]
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----
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ssw <sid>, <reg>, <sre>, <cmd>
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----
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+
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Where:
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[horizontal]
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sid:::
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The subsystem identifier.
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Should be in the range *ss0*..*ss15*.
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reg::: The _Execution Engine_ source register.
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sre:::
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The subsystem destination register.
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Should be in the range *sr0*..*sr255*.
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cmd::: The subsystem register specific command to use for writing.
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Examples::
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+
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[source]
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----
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ssw ss0, r1, sr0, 1 <1>
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ssw ss15, pc, sr32, 0 <2>
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----
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<1> Writes the value in *r1* into the *sr0* register from the *ss0* subsystem using the command _0x1_ to do so.
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<2> Writes the value in *pc* into the *sr32* register from the *ss15* subsystem using the command _0x0_ to do so.
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Privileged instruction:: No. (The access control is done at the register/command level).
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Updates program state flags:: No.
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Exceptions:: UnknownInstr.
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@ -104,5 +104,5 @@ Channel::
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This exception is generated when an I/O device communicates with the _Execution Engine_ through a channel.
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If data is passed alongside the exception then it is stored in main memory and ready to be read by the time this exception is generated.
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include::subsystems.adoc[]
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include::subsystems-intro.adoc[]
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12
src/execution-engine-spec/subsystems-intro.adoc
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12
src/execution-engine-spec/subsystems-intro.adoc
Normal file
@ -0,0 +1,12 @@
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[id=subsystems-intro]
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=== Subsystems
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Subsystems are extra components interacting with an _Execution Engine_.
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.Examples of functions of subsystems
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* Manage virtual memory and cache
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* Manage memory access rights
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* Manage Channel I/O
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* Debug the system
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A generic interface is provided to interact with the subsystems through the use of the `ssr` and `ssw` instructions.
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@ -1,14 +1,55 @@
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[id=subsystems-intro]
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=== Subsystems
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Subsystems are extra components interacting with an _Execution Engine_.
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[id=subsystems]
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== Subsystems
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=== Specified Subsystems
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.Examples of subsystems
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* Execution Engine State Sybsystem
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* Memory Management Subsystem
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* Cache Control Subsystem
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* Channel I/O Subsystem
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* Debugging Subsystem
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* Hardware Management Subsystem
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The {central-arch-name} allows up to 16 subystem identifiers. Not all of these identifiers are used currently.
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A generic interface is provided to interact with the subsystems through the use of the `ssr` and `ssw` instructions.
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.Subsystems that are specified
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[cols="1,2,3"]
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|===
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|ID |Name |Description
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|0
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|Execution Engine Control Subsystem
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|#TODO: Describe it.#
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|1
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|Memory & Cache Control Subsystem
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|#TODO: Describe it.#
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|2
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|Hardware Management Subsystem
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|#TODO: Describe it.#
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|3
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|Debugging Subsystem
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|#TODO: Describe it.# See <<debugging-subsystem>>.
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|4
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|Channel I/O Subsystem
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|#TODO: Describe it.#
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|===
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[id=debugging-subsystem]
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=== Debugging Subsystem
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==== Description
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#TODO: Describe it.#
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==== Registers / Commands
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===== sr0: Simulation Control
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The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes.
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Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *UnknownInstr* exception if it happens.
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[source]
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----
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ssr ss3, r0, sr0, 0 <1>
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ssw ss3, r0, sr0, 0 <2>
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----
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<1> Read the Simulation Control register.
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<2> Write in the Simulation Control register.
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The register contains the value 1 when under simulation and 0 otherwise.
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Writing any value to it while under simulation has the effect of ending the simulation.
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