From ab401b9d1b2b998f5ea02e64e668513e8cd221cd Mon Sep 17 00:00:00 2001 From: Elyan Date: Thu, 31 Oct 2024 00:53:06 +0100 Subject: [PATCH] Added ssr/ssw instructions and added subsystems information --- src/central-execution-engine-spec.adoc | 3 +- .../instructions-operands-encoding.adoc | 51 ++++++++ src/execution-engine-spec/instructions.adoc | 120 ++++++++++++++++-- src/execution-engine-spec/intro.adoc | 2 +- .../subsystems-intro.adoc | 12 ++ src/execution-engine-spec/subsystems.adoc | 63 +++++++-- 6 files changed, 229 insertions(+), 22 deletions(-) create mode 100644 src/execution-engine-spec/subsystems-intro.adoc diff --git a/src/central-execution-engine-spec.adoc b/src/central-execution-engine-spec.adoc index dc42f33..061e04c 100644 --- a/src/central-execution-engine-spec.adoc +++ b/src/central-execution-engine-spec.adoc @@ -10,4 +10,5 @@ include::execution-engine-spec/glossary.adoc[] include::execution-engine-spec/intro.adoc[] include::execution-engine-spec/program-and-exception-status-registers.adoc[] include::execution-engine-spec/channel-io-overview.adoc[] -include::execution-engine-spec/instructions.adoc[] \ No newline at end of file +include::execution-engine-spec/instructions.adoc[] +include::execution-engine-spec/subsystems.adoc[] \ No newline at end of file diff --git a/src/execution-engine-spec/instructions-operands-encoding.adoc b/src/execution-engine-spec/instructions-operands-encoding.adoc index cbda4fd..bf8c3df 100644 --- a/src/execution-engine-spec/instructions-operands-encoding.adoc +++ b/src/execution-engine-spec/instructions-operands-encoding.adoc @@ -192,3 +192,54 @@ |sp_fault |=== + +[id=subsystems-encoding] +==== Subsystems Encoding + +[%header,cols="^1,^1,2"] +|=== +2+|Value +|Name + +|0000~2~ +|0000~16~ +|ss0 + +|0001~2~ +|0001~16~ +|ss1 + +|0010~2~ .. 1110~2~ +|0002~16~ .. 000e~16~ +|ss2 .. ss14 + +|1111~2~ +|000f~16~ +|ss15 +|=== + +[id=subsystems-registers-encoding] +==== Subsystems Registers Encoding + +[%header,cols="^1,^1,2"] +|=== +2+|Value +|Name + +|00000000~2~ +|00000000~16~ +|sr0 + +|00000001~2~ +|00000001~16~ +|sr1 + +|00000010~2~ .. 11111110~2~ +|00000002~16~ .. 000000fe~16~ +|sr2 .. sr254 + +|11111111~2~ +|000000ff~16~ +|sr255 +|=== + diff --git a/src/execution-engine-spec/instructions.adoc b/src/execution-engine-spec/instructions.adoc index 360be3a..1fc8211 100644 --- a/src/execution-engine-spec/instructions.adoc +++ b/src/execution-engine-spec/instructions.adoc @@ -23,21 +23,25 @@ rs1:: rs2:: Source register 2. imm:: - Immediate value. + Immediate value. + Can be interpreted as signed or unsigned depending on the instruction. reg:: - Source/destination register on the _Execution Engine_ side. + Source/destination register on the _Execution Engine_ side. + + See <>. sid:: - Subsystem ID. + Subsystem ID. + + See <>. sre:: - Source/destination register on the subsystem side. + Source/destination register on the subsystem side. + + See <>. cmd:: - Subsystem command. + Subsystem register command. + + Specific to the accessed subsystem register. More info in <>. include::instructions-operands-encoding.adoc[] <<< -=== Instruction list +=== Instruction List #TODO: List instructions# * NOP instruction @@ -50,7 +54,7 @@ include::instructions-operands-encoding.adoc[] * system mode instructions (svc, uret, sret, ...) * subsystems instructions (ssr & ssw) -==== Miscellaneous instructions +==== Miscellaneous Instructions ===== NOP: No Operation [wavedrom, ,svg] .... @@ -78,7 +82,7 @@ Exceptions:: None. [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 0x7f, type: 8, attr: '0x7f'}, + {bits: 7, name: 0x7f, type: 8, attr: '0x7e'}, {bits: 25, name: 'svc_num', type: 5} ], config: {label: {right: 'SVC'}}} .... @@ -97,7 +101,7 @@ Where: [horizontal] svc_num::: A constant identifying the privileged operation to execute. + - Must be in the range 0-33554431 (0x0-0x1FFFFFF). + Must be in the range 0..33554431 (0x0..0x1FFFFFF). Examples:: + @@ -439,3 +443,101 @@ Updates program state flags:: No. Exceptions:: MemFault. + +<<< +==== Subsystems Instructions +===== SSR: Subsystem Register Read +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x7d, type: 8, attr: '0x7d'}, + {bits: 5, name: 'reg', type: 2}, + {bits: 4, name: 'sid', type: 7}, + {bits: 8, name: 'sre', type: 2}, + {bits: 8, name: 'cmd', type: 8} +], config: {label: {right: 'SSR'}}} +.... + +Description:: + Reads a value from a subsystem register into an _Execution Engine_ register. +Encoding:: E-Type +Assembler syntax:: ++ +[source] +---- +ssr , , , +---- ++ +Where: +[horizontal] +sid::: + The subsystem identifier. + Should be in the range *ss0*..*ss15*. +reg::: The _Execution Engine_ destination register. +sre::: + The subsystem source register. + Should be in the range *sr0*..*sr255*. +cmd::: The subsystem register specific command to use for reading. + +Examples:: ++ +[source] +---- +ssr ss0, r1, sr0, 1 <1> +ssr ss15, pc, sr32, 0 <2> +---- +<1> Reads the *sr0* register from the *ss0* subsystem into *r1* using the command _0x1_ to do so. +<2> Reads the *sr32* register from the *ss15* subsystem into *pc* using the command _0x0_ to do so. + +Privileged instruction:: No. (The access control is done at the register/command level). +Updates program state flags:: No. +Exceptions:: UnknownInstr. + +<<< +===== SSW: Subsystem Register Write +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x7e, type: 8, attr: '0x7e'}, + {bits: 5, name: 'reg', type: 2}, + {bits: 4, name: 'sid', type: 7}, + {bits: 8, name: 'sre', type: 2}, + {bits: 8, name: 'cmd', type: 8} +], config: {label: {right: 'SSW'}}} +.... + +Description:: + Writes a value from an _Execution Engine_ register into a subsystem register. +Encoding:: E-Type +Assembler syntax:: ++ +[source] +---- +ssw , , , +---- ++ +Where: +[horizontal] +sid::: + The subsystem identifier. + Should be in the range *ss0*..*ss15*. +reg::: The _Execution Engine_ source register. +sre::: + The subsystem destination register. + Should be in the range *sr0*..*sr255*. +cmd::: The subsystem register specific command to use for writing. + +Examples:: ++ +[source] +---- +ssw ss0, r1, sr0, 1 <1> +ssw ss15, pc, sr32, 0 <2> +---- +<1> Writes the value in *r1* into the *sr0* register from the *ss0* subsystem using the command _0x1_ to do so. +<2> Writes the value in *pc* into the *sr32* register from the *ss15* subsystem using the command _0x0_ to do so. + +Privileged instruction:: No. (The access control is done at the register/command level). +Updates program state flags:: No. +Exceptions:: UnknownInstr. + diff --git a/src/execution-engine-spec/intro.adoc b/src/execution-engine-spec/intro.adoc index a8fdf43..6f5ab4c 100644 --- a/src/execution-engine-spec/intro.adoc +++ b/src/execution-engine-spec/intro.adoc @@ -104,5 +104,5 @@ Channel:: This exception is generated when an I/O device communicates with the _Execution Engine_ through a channel. If data is passed alongside the exception then it is stored in main memory and ready to be read by the time this exception is generated. -include::subsystems.adoc[] +include::subsystems-intro.adoc[] diff --git a/src/execution-engine-spec/subsystems-intro.adoc b/src/execution-engine-spec/subsystems-intro.adoc new file mode 100644 index 0000000..8de4ffa --- /dev/null +++ b/src/execution-engine-spec/subsystems-intro.adoc @@ -0,0 +1,12 @@ +[id=subsystems-intro] +=== Subsystems +Subsystems are extra components interacting with an _Execution Engine_. + +.Examples of functions of subsystems +* Manage virtual memory and cache +* Manage memory access rights +* Manage Channel I/O +* Debug the system + +A generic interface is provided to interact with the subsystems through the use of the `ssr` and `ssw` instructions. + diff --git a/src/execution-engine-spec/subsystems.adoc b/src/execution-engine-spec/subsystems.adoc index 4e59301..dccfa7f 100644 --- a/src/execution-engine-spec/subsystems.adoc +++ b/src/execution-engine-spec/subsystems.adoc @@ -1,14 +1,55 @@ -[id=subsystems-intro] -=== Subsystems -Subsystems are extra components interacting with an _Execution Engine_. +[id=subsystems] +== Subsystems +=== Specified Subsystems -.Examples of subsystems -* Execution Engine State Sybsystem -* Memory Management Subsystem -* Cache Control Subsystem -* Channel I/O Subsystem -* Debugging Subsystem -* Hardware Management Subsystem +The {central-arch-name} allows up to 16 subystem identifiers. Not all of these identifiers are used currently. -A generic interface is provided to interact with the subsystems through the use of the `ssr` and `ssw` instructions. +.Subsystems that are specified +[cols="1,2,3"] +|=== +|ID |Name |Description + +|0 +|Execution Engine Control Subsystem +|#TODO: Describe it.# + +|1 +|Memory & Cache Control Subsystem +|#TODO: Describe it.# + +|2 +|Hardware Management Subsystem +|#TODO: Describe it.# + +|3 +|Debugging Subsystem +|#TODO: Describe it.# See <>. + +|4 +|Channel I/O Subsystem +|#TODO: Describe it.# +|=== + + +[id=debugging-subsystem] +=== Debugging Subsystem +==== Description +#TODO: Describe it.# + +==== Registers / Commands +===== sr0: Simulation Control + +The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes. +Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *UnknownInstr* exception if it happens. + +[source] +---- +ssr ss3, r0, sr0, 0 <1> +ssw ss3, r0, sr0, 0 <2> +---- +<1> Read the Simulation Control register. +<2> Write in the Simulation Control register. + +The register contains the value 1 when under simulation and 0 otherwise. +Writing any value to it while under simulation has the effect of ending the simulation.