Added ldrh and ldrc instructions
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@ -30,6 +30,10 @@ include::instructions/svc.adoc[]
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<<<
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==== Memory-Related Instructions
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include::instructions/ldr.adoc[]
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<<<
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include::instructions/ldrh.adoc[]
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<<<
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include::instructions/ldrc.adoc[]
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<<<
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==== Register Manipulation Instructions
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106
src/execution-engine-spec/instructions/ldrc.adoc
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106
src/execution-engine-spec/instructions/ldrc.adoc
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@ -0,0 +1,106 @@
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===== LDRC: Load Register Character
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x3, type: 8, attr: '0x03'},
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{bits: 4, name: 'off[3:0]', type: 5},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off[14:4]', type: 5}
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], config: {label: {right: 'LDRCI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x6, type: 8, attr: '0x06'},
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{bits: 4, name: 'unused'},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDRCR'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|LDRCI
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|<<LDRCI>>
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|LDRCR
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|<<LDRCR>>
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|===
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<<<
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[id=LDRCI]
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====== LDRCI: Load Character Register+Immediate
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Description::
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Loads a character (or byte) from memory into a register.
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The immediate offset `off` is added to the address in the `src` register before reading memory.
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Encoding:: B1-Type
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Assembler syntax::
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+
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[source]
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----
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ldrc <dst>, [<src>, <off?>]
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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src::: Source register.
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off:::
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Optional offset immediate.
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Must be in the range -16384..16383.
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If omitted, then 0 is used.
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Examples::
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+
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[source]
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----
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ldrc r1, [r0] <1>
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ldrc r3, [r2, 8] <2>
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----
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<1> Reads a character from the memory address in r0 into r1.
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<2> Reads a character from the memory address in r2, with an 8 bytes offset, into r3.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=LDRCR]
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====== LDRCR: Load Character Register+Register
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Description::
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Loads a character (or byte) from memory into a register.
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The value in the register `off` is added to the address in the `src` register before reading memory.
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Encoding:: A1-Type
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Assembler syntax::
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+
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[source]
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----
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ldrc <dst>, [<src>, <off>]
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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src::: Source register.
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off::: Offset register.
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Examples::
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+
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[source]
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----
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ldrc r1, [sp, r0] <1>
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----
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<1> Reads a character from the memory address in sp into r1, using the value of r0 as an offset.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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106
src/execution-engine-spec/instructions/ldrh.adoc
Normal file
106
src/execution-engine-spec/instructions/ldrh.adoc
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@ -0,0 +1,106 @@
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===== LDRH: Load Register Halfword
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x2, type: 8, attr: '0x02'},
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{bits: 4, name: 'off[3:0]', type: 5},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off[14:4]', type: 5}
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], config: {label: {right: 'LDRHI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x5, type: 8, attr: '0x05'},
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{bits: 4, name: 'unused'},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDRHR'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|LDRHI
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|<<LDRHI>>
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|LDRHR
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|<<LDRHR>>
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|===
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<<<
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[id=LDRHI]
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====== LDRHI: Load Halfword Register+Immediate
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Description::
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Loads a halfword from memory into a register.
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The immediate offset `off` is added to the address in the `src` register before reading memory.
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Encoding:: B1-Type
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Assembler syntax::
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+
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[source]
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----
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ldrh <dst>, [<src>, <off?>]
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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src::: Source register.
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off:::
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Optional offset immediate.
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Must be a multiple of 2 and in the range -32768..32766.
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If omitted, then 0 is used.
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Examples::
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+
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[source]
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----
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ldrh r1, [r0] <1>
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ldrh r3, [r2, 8] <2>
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----
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<1> Reads a halfword from the memory address in r0 into r1.
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<2> Reads a halfword from the memory address in r2, with an 8 bytes offset, into r3.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=LDRHR]
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====== LDRHR: Load Halfword Register+Register
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Description::
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Loads a halfword from memory into a register.
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The value in the register `off` is added to the address in the `src` register before reading memory.
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Encoding:: A1-Type
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Assembler syntax::
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+
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[source]
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----
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ldrh <dst>, [<src>, <off>]
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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src::: Source register.
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off::: Offset register.
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Examples::
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+
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[source]
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----
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ldrh r1, [sp, r0] <1>
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----
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<1> Reads a halfword from the memory address in sp into r1, using the value of r0 as an offset.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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