diff --git a/src/execution-engine-spec/instructions.adoc b/src/execution-engine-spec/instructions.adoc index 5b8ed75..cb8d84c 100644 --- a/src/execution-engine-spec/instructions.adoc +++ b/src/execution-engine-spec/instructions.adoc @@ -30,6 +30,10 @@ include::instructions/svc.adoc[] <<< ==== Memory-Related Instructions include::instructions/ldr.adoc[] +<<< +include::instructions/ldrh.adoc[] +<<< +include::instructions/ldrc.adoc[] <<< ==== Register Manipulation Instructions diff --git a/src/execution-engine-spec/instructions/b.adoc b/src/execution-engine-spec/instructions/b.adoc index d6c7751..d8ca91e 100644 --- a/src/execution-engine-spec/instructions/b.adoc +++ b/src/execution-engine-spec/instructions/b.adoc @@ -54,7 +54,7 @@ Examples:: [source] ---- b.ne -20 <1> -b.eq 8 <2> +b.eq 8 <2> ---- <1> If the last comparison resulted in an 'ne' condition status, branches to `pc - 20`. Else, does nothing. <2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8`. Else, does nothing. @@ -90,7 +90,7 @@ Examples:: + [source] ---- -b -0x3FFFFF <1> +b -0x3FFFFF <1> b.al 0x3FFFFF <2> ---- <1> Branches to `pc - 0x3FFFFF`. diff --git a/src/execution-engine-spec/instructions/bx.adoc b/src/execution-engine-spec/instructions/bx.adoc index 6fea878..ecbac02 100644 --- a/src/execution-engine-spec/instructions/bx.adoc +++ b/src/execution-engine-spec/instructions/bx.adoc @@ -61,7 +61,7 @@ Examples:: [source] ---- bx [r0, 12] <1> -bx.eq [r3] <2> +bx.eq [r3] <2> ---- <1> Branches to the instruction at address `r0 + 12`. <2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing. @@ -95,7 +95,7 @@ Examples:: + [source] ---- -bx [r0, r1] <1> +bx [r0, r1] <1> bx.eq [r2, r3] <2> ---- <1> Branches to the instruction at address `r0 + r1`. diff --git a/src/execution-engine-spec/instructions/ldrc.adoc b/src/execution-engine-spec/instructions/ldrc.adoc new file mode 100644 index 0000000..2bbfb42 --- /dev/null +++ b/src/execution-engine-spec/instructions/ldrc.adoc @@ -0,0 +1,106 @@ +===== LDRC: Load Register Character +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x3, type: 8, attr: '0x03'}, + {bits: 4, name: 'off[3:0]', type: 5}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off[14:4]', type: 5} +], config: {label: {right: 'LDRCI'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x6, type: 8, attr: '0x06'}, + {bits: 4, name: 'unused'}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDRCR'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|LDRCI +|<> + +|LDRCR +|<> +|=== + +<<< +[id=LDRCI] +====== LDRCI: Load Character Register+Immediate +Description:: + Loads a character (or byte) from memory into a register. + The immediate offset `off` is added to the address in the `src` register before reading memory. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +ldrc , [, ] +---- ++ +Where: +[horizontal] +dst::: Destination register. +src::: Source register. +off::: + Optional offset immediate. + Must be in the range -16384..16383. + If omitted, then 0 is used. + +Examples:: ++ +[source] +---- +ldrc r1, [r0] <1> +ldrc r3, [r2, 8] <2> +---- +<1> Reads a character from the memory address in r0 into r1. +<2> Reads a character from the memory address in r2, with an 8 bytes offset, into r3. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=LDRCR] +====== LDRCR: Load Character Register+Register +Description:: + Loads a character (or byte) from memory into a register. + The value in the register `off` is added to the address in the `src` register before reading memory. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +ldrc , [, ] +---- ++ +Where: +[horizontal] +dst::: Destination register. +src::: Source register. +off::: Offset register. + +Examples:: ++ +[source] +---- +ldrc r1, [sp, r0] <1> +---- +<1> Reads a character from the memory address in sp into r1, using the value of r0 as an offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + diff --git a/src/execution-engine-spec/instructions/ldrh.adoc b/src/execution-engine-spec/instructions/ldrh.adoc new file mode 100644 index 0000000..9934495 --- /dev/null +++ b/src/execution-engine-spec/instructions/ldrh.adoc @@ -0,0 +1,106 @@ +===== LDRH: Load Register Halfword +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x2, type: 8, attr: '0x02'}, + {bits: 4, name: 'off[3:0]', type: 5}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off[14:4]', type: 5} +], config: {label: {right: 'LDRHI'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x5, type: 8, attr: '0x05'}, + {bits: 4, name: 'unused'}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDRHR'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|LDRHI +|<> + +|LDRHR +|<> +|=== + +<<< +[id=LDRHI] +====== LDRHI: Load Halfword Register+Immediate +Description:: + Loads a halfword from memory into a register. + The immediate offset `off` is added to the address in the `src` register before reading memory. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +ldrh , [, ] +---- ++ +Where: +[horizontal] +dst::: Destination register. +src::: Source register. +off::: + Optional offset immediate. + Must be a multiple of 2 and in the range -32768..32766. + If omitted, then 0 is used. + +Examples:: ++ +[source] +---- +ldrh r1, [r0] <1> +ldrh r3, [r2, 8] <2> +---- +<1> Reads a halfword from the memory address in r0 into r1. +<2> Reads a halfword from the memory address in r2, with an 8 bytes offset, into r3. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=LDRHR] +====== LDRHR: Load Halfword Register+Register +Description:: + Loads a halfword from memory into a register. + The value in the register `off` is added to the address in the `src` register before reading memory. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +ldrh , [, ] +---- ++ +Where: +[horizontal] +dst::: Destination register. +src::: Source register. +off::: Offset register. + +Examples:: ++ +[source] +---- +ldrh r1, [sp, r0] <1> +---- +<1> Reads a halfword from the memory address in sp into r1, using the value of r0 as an offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + diff --git a/src/execution-engine-spec/instructions/movn.adoc b/src/execution-engine-spec/instructions/movn.adoc index 69654e9..54d5dd0 100644 --- a/src/execution-engine-spec/instructions/movn.adoc +++ b/src/execution-engine-spec/instructions/movn.adoc @@ -35,7 +35,7 @@ Examples:: + [source] ---- -movn r0, -42 <1> +movn r0, -42 <1> movn r0, 0x10 <2> ---- <1> Sets r0 to -42. diff --git a/src/execution-engine-spec/instructions/ssr.adoc b/src/execution-engine-spec/instructions/ssr.adoc index f02ceab..79810e7 100644 --- a/src/execution-engine-spec/instructions/ssr.adoc +++ b/src/execution-engine-spec/instructions/ssr.adoc @@ -36,7 +36,7 @@ Examples:: + [source] ---- -ssr ss0, r1, sr0, 1 <1> +ssr ss0, r1, sr0, 1 <1> ssr ss15, pc, sr32, 0 <2> ---- <1> Reads the sr0 register from the ss0 subsystem into r1 using the command _0x1_ to do so. diff --git a/src/execution-engine-spec/instructions/ssw.adoc b/src/execution-engine-spec/instructions/ssw.adoc index d394c43..578bdeb 100644 --- a/src/execution-engine-spec/instructions/ssw.adoc +++ b/src/execution-engine-spec/instructions/ssw.adoc @@ -36,7 +36,7 @@ Examples:: + [source] ---- -ssw ss0, r1, sr0, 1 <1> +ssw ss0, r1, sr0, 1 <1> ssw ss15, pc, sr32, 0 <2> ---- <1> Writes the value in r1 into the sr0 register from the ss0 subsystem using the command _0x1_ to do so.