Split the instructions in multiple files and added move and branch instructions
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Central(Architecture) Docs Build / Build Documentation (push) Successful in 17s
This commit is contained in:
parent
3459319b1a
commit
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@ -1,60 +0,0 @@
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 5, name: 'rs2', type: 4},
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{bits: 6, name: 'imm', type: 5}
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], config: {label: {right: 'A-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 11, name: 'imm', type: 5}
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], config: {label: {right: 'B-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 16, name: 'imm', type: 5}
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], config: {label: {right: 'C-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 21, name: 'imm', type: 5}
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], config: {label: {right: 'D1-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 25, name: 'imm', type: 5}
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], config: {label: {right: 'D2-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 5, name: 'reg', type: 2},
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{bits: 4, name: 'sid', type: 7},
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{bits: 8, name: 'sre', type: 2},
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{bits: 8, name: 'cmd', type: 8}
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], config: {label: {right: 'E-Type'}}}
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....
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115
src/execution-engine-spec/instruction-formats.adoc
Normal file
115
src/execution-engine-spec/instruction-formats.adoc
Normal file
@ -0,0 +1,115 @@
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 5, name: 'rs2', type: 4},
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{bits: 6, name: 'imm', type: 5}
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], config: {label: {right: 'A1-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'imm[4:0]', type: 5},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 5, name: 'rs2', type: 4},
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{bits: 6, name: 'imm[10:5]', type: 5}
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], config: {label: {right: 'A2-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 11, name: 'imm', type: 5}
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], config: {label: {right: 'B1-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'imm[4:0]', type: 5},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 11, name: 'imm[15:5]', type: 5}
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], config: {label: {right: 'B2-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 16, name: 'imm', type: 5}
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], config: {label: {right: 'C-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 21, name: 'imm', type: 5}
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], config: {label: {right: 'D1-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 1, name: 0},
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{bits: 24, name: 'imm', type: 5}
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], config: {label: {right: 'D2-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 5, name: 'reg', type: 2},
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{bits: 4, name: 'sid', type: 7},
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{bits: 8, name: 'sre', type: 2},
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{bits: 8, name: 'cmd', type: 8}
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], config: {label: {right: 'E-Type'}}}
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....
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.Format fields
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[horizontal]
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opcode::
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The operation to carry on.
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cond::
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Condition code. +
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See <<conditions-encoding>>.
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rd::
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Destination register. +
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See <<registers-encoding>>.
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rs1::
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Source register 1.
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rs2::
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Source register 2.
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imm::
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Immediate value. +
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Can be interpreted as signed or unsigned depending on the instruction.
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reg::
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Source/destination register on the _Execution Engine_ side. +
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See <<registers-encoding>>.
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sid::
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Subsystem ID. +
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See <<subsystems-encoding>>.
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sre::
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Source/destination register on the subsystem side. +
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See <<subsystems-registers-encoding>>.
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cmd::
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Subsystem register command. +
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Specific to the accessed subsystem register. More info in <<subsystems>>.
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@ -6,538 +6,41 @@ The source (rs1 and rs2) and destination (rd) registers are kept at the same pos
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For instruction encoding formats that contain an immediate value, not all immediate bits are used by all instructions sharing the format. The actual relevant bits are specified for these instructions.
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For instruction encoding formats that contain an immediate value, not all immediate bits are used by all instructions sharing the format. The actual relevant bits are specified for these instructions.
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include::images/instruction-formats.adoc[]
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include::instruction-formats.adoc[]
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<<<
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.Format fields
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[horizontal]
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opcode::
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The operation to carry on.
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cond::
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Condition code. +
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See <<conditions-encoding>>.
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rd::
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Destination register. +
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See <<registers-encoding>>.
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rs1::
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Source register 1.
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rs2::
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Source register 2.
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imm::
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Immediate value. +
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Can be interpreted as signed or unsigned depending on the instruction.
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reg::
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Source/destination register on the _Execution Engine_ side. +
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See <<registers-encoding>>.
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sid::
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Subsystem ID. +
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See <<subsystems-encoding>>.
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sre::
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Source/destination register on the subsystem side. +
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See <<subsystems-registers-encoding>>.
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cmd::
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Subsystem register command. +
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Specific to the accessed subsystem register. More info in <<subsystems>>.
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include::instructions-operands-encoding.adoc[]
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include::instructions-operands-encoding.adoc[]
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<<<
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<<<
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=== Instruction List
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=== Instruction List
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#TODO: List instructions#
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#TODO: List instructions#
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* NOP instruction
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* memory load/store instructions
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* memory load/store instructions
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* register move instructions
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* arithmetic instructions
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* arithmetic instructions
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* bitwise operations instructions (w/ bit shifts)
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* bitwise operations instructions (w/ bit shifts)
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* comparison instructions
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* comparison instructions
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* jump instructions
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* jump instructions
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* system mode instructions (svc, uret, sret, ...)
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* system mode instructions (svc, uret, sret, ...)
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* subsystems instructions (ssr & ssw)
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==== Miscellaneous Instructions
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==== Miscellaneous Instructions
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===== NOP: No Operation
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include::instructions/nop.adoc[]
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[wavedrom, ,svg]
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<<<
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....
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include::instructions/svc.adoc[]
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{reg: [
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{bits: 7, name: 0x0, type: 8, attr: '0x0'},
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{bits: 25, name: 'unused'}
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], config: {label: {right: 'NOP'}}}
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....
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Description::
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Does nothing. Can be used to align a block of instructions.
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Encoding:: D2-Type
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Assembler syntax::
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+
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[source]
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----
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nop
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----
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions:: None.
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<<<
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<<<
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===== SVC: Supervisor Call
|
==== Memory-Related Instructions
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[wavedrom, ,svg]
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include::instructions/ldr.adoc[]
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....
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{reg: [
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{bits: 7, name: 0x7f, type: 8, attr: '0x7e'},
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{bits: 25, name: 'svc_num', type: 5}
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], config: {label: {right: 'SVC'}}}
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....
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|
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Description::
|
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Generates an SVC exception to execute a privileged operation.
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Encoding:: D2-Type
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Assembler syntax::
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+
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[source]
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----
|
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svc <svc_num>
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----
|
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+
|
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Where:
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[horizontal]
|
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svc_num:::
|
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A constant identifying the privileged operation to execute. +
|
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Must be in the range 0..33554431 (0x0..0x1FFFFFF).
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Examples::
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+
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[source]
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----
|
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svc 128 <1>
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svc 0xff <2>
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----
|
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<1> Calls the privileged operation number 128 that is exposed by the kernel.
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<2> Calls the privileged operation number 255 that is exposed by the kernel.
|
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|
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Privileged instruction:: No.
|
|
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Updates program state flags:: No.
|
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Exceptions:: SVC.
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|
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<<<
|
<<<
|
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==== Memory-related instructions
|
==== Register Manipulation Instructions
|
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===== LDR: Load Register
|
include::instructions/mov.adoc[]
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x1, type: 8, attr: '0x1'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIR'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x2, type: 8, attr: '0x2'},
|
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{bits: 4, name: 'cond', type: 6},
|
|
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{bits: 5, name: 'dst', type: 2},
|
|
||||||
{bits: 5, name: 'src', type: 4},
|
|
||||||
{bits: 11, name: 'off', type: 5}
|
|
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], config: {label: {right: 'LDRIRW'}}}
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....
|
|
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|
|
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[wavedrom, ,svg]
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|
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....
|
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{reg: [
|
|
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{bits: 7, name: 0x3, type: 8, attr: '0x3'},
|
|
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{bits: 4, name: 'cond', type: 6},
|
|
||||||
{bits: 5, name: 'dst', type: 2},
|
|
||||||
{bits: 5, name: 'src', type: 4},
|
|
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{bits: 11, name: 'off', type: 5}
|
|
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], config: {label: {right: 'LDRIOW'}}}
|
|
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....
|
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|
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[wavedrom, ,svg]
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|
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....
|
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{reg: [
|
|
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{bits: 7, name: 0x4, type: 8, attr: '0x4'},
|
|
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{bits: 4, name: 'cond', type: 6},
|
|
||||||
{bits: 5, name: 'dst', type: 2},
|
|
||||||
{bits: 5, name: 'src', type: 4},
|
|
||||||
{bits: 5, name: 'off', type: 4},
|
|
||||||
{bits: 6, name: 'unused'}
|
|
||||||
], config: {label: {right: 'LDRR'}}}
|
|
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....
|
|
||||||
|
|
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[wavedrom, ,svg]
|
|
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....
|
|
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{reg: [
|
|
||||||
{bits: 7, name: 0x5, type: 8, attr: '0x5'},
|
|
||||||
{bits: 4, name: 'cond', type: 6},
|
|
||||||
{bits: 5, name: 'dst', type: 2},
|
|
||||||
{bits: 5, name: 'src', type: 4},
|
|
||||||
{bits: 5, name: 'off', type: 4},
|
|
||||||
{bits: 6, name: 'unused'}
|
|
||||||
], config: {label: {right: 'LDRRW'}}}
|
|
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....
|
|
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|
|
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[wavedrom, ,svg]
|
|
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....
|
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{reg: [
|
|
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{bits: 7, name: 0x6, type: 8, attr: '0x6'},
|
|
||||||
{bits: 4, name: 'cond', type: 6},
|
|
||||||
{bits: 5, name: 'dst', type: 2},
|
|
||||||
{bits: 5, name: 'src', type: 4},
|
|
||||||
{bits: 5, name: 'off', type: 4},
|
|
||||||
{bits: 6, name: 'unused'}
|
|
||||||
], config: {label: {right: 'LDROW'}}}
|
|
||||||
....
|
|
||||||
|
|
||||||
[frame=ends,grid=rows,cols="1,1"]
|
|
||||||
|===
|
|
||||||
|Instruction variant | Description
|
|
||||||
|
|
||||||
|LDRIR
|
|
||||||
|<<LDRIR>>
|
|
||||||
|
|
||||||
|LDRIRW
|
|
||||||
|<<LDRIRW>>
|
|
||||||
|
|
||||||
|LDRIOW
|
|
||||||
|<<LDRIOW>>
|
|
||||||
|
|
||||||
|LDRR
|
|
||||||
|<<LDRR>>
|
|
||||||
|
|
||||||
|LDRRW
|
|
||||||
|<<LDRRW>>
|
|
||||||
|
|
||||||
|LDROW
|
|
||||||
|<<LDROW>>
|
|
||||||
|===
|
|
||||||
|
|
||||||
<<<
|
<<<
|
||||||
[id=LDRIR]
|
==== Branching Instructions
|
||||||
====== LDRIR: Load Register+Immediate Pre-indexed
|
include::instructions/b.adoc[]
|
||||||
Description::
|
|
||||||
Loads a word from memory into a register.
|
|
||||||
The immediate offset `off` is added to the address in the `src` register before reading memory.
|
|
||||||
Encoding:: A-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr<cond?> <dst>, [<src>, <off?>]
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
cond::: Optional condition.
|
|
||||||
dst::: Destination register.
|
|
||||||
src::: Source register.
|
|
||||||
off:::
|
|
||||||
Optional offset immediate.
|
|
||||||
Must be a multiple of 4 and in the range 0-8188.
|
|
||||||
If omitted, then 0 is used.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr r1, [r0] <1>
|
|
||||||
ldr r3, [r2, 8] <2>
|
|
||||||
ldr.eq r5, [r4] <3>
|
|
||||||
----
|
|
||||||
<1> Reads a word from the memory address in r0 into r1.
|
|
||||||
<2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3.
|
|
||||||
<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing.
|
|
||||||
|
|
||||||
Privileged instruction:: No.
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions::
|
|
||||||
MemFault.
|
|
||||||
|
|
||||||
<<<
|
|
||||||
[id=LDRIRW]
|
|
||||||
====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back
|
|
||||||
Description::
|
|
||||||
Increments the source register then reads a word from memory into the destination register.
|
|
||||||
The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register.
|
|
||||||
Encoding:: A-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr<cond?> <dst>, ![<src>, <off?>]
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
cond::: Optional condition.
|
|
||||||
dst::: Destination register.
|
|
||||||
src::: Source register.
|
|
||||||
off:::
|
|
||||||
Optional offset immediate.
|
|
||||||
Must be a multiple of 4 and in the range 0-8188.
|
|
||||||
If omitted, then 4 is used.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr r1, ![r0] <1>
|
|
||||||
ldr r3, ![r2, 8] <2>
|
|
||||||
ldr.eq r5, ![r4] <3>
|
|
||||||
----
|
|
||||||
<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1.
|
|
||||||
<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3.
|
|
||||||
<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing.
|
|
||||||
|
|
||||||
Privileged instruction:: No.
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions::
|
|
||||||
MemFault.
|
|
||||||
|
|
||||||
<<<
|
|
||||||
[id=LDRIOW]
|
|
||||||
====== LDRIOW: Load Register+Immediate Post-indexed with Write-back
|
|
||||||
Description::
|
|
||||||
Reads a word from memory into the destination register then increments the source register.
|
|
||||||
The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`.
|
|
||||||
Encoding:: A-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr<cond?> <dst>, [<src>, <off?>]!
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
cond::: Optional condition.
|
|
||||||
dst::: Destination register.
|
|
||||||
src::: Source register.
|
|
||||||
off:::
|
|
||||||
Optional offset immediate.
|
|
||||||
Must be a multiple of 4 and in the range 0-8188.
|
|
||||||
If omitted, then 4 is used.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr r1, [r0]! <1>
|
|
||||||
ldr r3, [r2, 8]! <2>
|
|
||||||
ldr.eq r5, [r4]! <3>
|
|
||||||
----
|
|
||||||
<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4.
|
|
||||||
<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8.
|
|
||||||
<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing.
|
|
||||||
|
|
||||||
Privileged instruction:: No.
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions::
|
|
||||||
MemFault.
|
|
||||||
|
|
||||||
<<<
|
|
||||||
[id=LDRR]
|
|
||||||
====== LDRR: Load Register+Register Pre-indexed
|
|
||||||
Description::
|
|
||||||
Loads a word from memory into a register.
|
|
||||||
The value in the register `off` is added to the address in the `src` register before reading memory.
|
|
||||||
Encoding:: A-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr<cond?> <dst>, [<src>, <off>]
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
cond::: Optional condition.
|
|
||||||
dst::: Destination register.
|
|
||||||
src::: Source register.
|
|
||||||
off::: Offset register.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr r1, [sp, r0] <1>
|
|
||||||
ldr.eq r0, [r1, r2] <2>
|
|
||||||
----
|
|
||||||
<1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset.
|
|
||||||
<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing.
|
|
||||||
|
|
||||||
Privileged instruction:: No.
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions::
|
|
||||||
MemFault.
|
|
||||||
|
|
||||||
<<<
|
|
||||||
[id=LDRRW]
|
|
||||||
====== LDRRW: Load Register+Register Pre-indexed with Write-back
|
|
||||||
Description::
|
|
||||||
Increments the source register then reads a word from memory into the destination register.
|
|
||||||
The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register.
|
|
||||||
Encoding:: A-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr<cond?> <dst>, ![<src>, <off>]
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
cond::: Optional condition.
|
|
||||||
dst::: Destination register.
|
|
||||||
src::: Source register.
|
|
||||||
off::: Offset register.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr r1, ![sp, r0] <1>
|
|
||||||
ldr.eq r0, ![r1, r2] <2>
|
|
||||||
----
|
|
||||||
<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1.
|
|
||||||
<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing.
|
|
||||||
|
|
||||||
Privileged instruction:: No.
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions::
|
|
||||||
MemFault.
|
|
||||||
|
|
||||||
<<<
|
|
||||||
[id=LDROW]
|
|
||||||
====== LDROW: Load Register+Register Post-indexed with Write-back
|
|
||||||
Description::
|
|
||||||
Reads a word from memory into the destination register then increments the source register.
|
|
||||||
The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`.
|
|
||||||
Encoding:: A-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr<cond?> <dst>, [<src>, <off>]!
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
cond::: Optional condition.
|
|
||||||
dst::: Destination register.
|
|
||||||
src::: Source register.
|
|
||||||
off::: Offset register.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ldr r1, [sp, r0]! <1>
|
|
||||||
ldr.eq r0, [r1, r2]! <2>
|
|
||||||
----
|
|
||||||
<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp.
|
|
||||||
<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing.
|
|
||||||
|
|
||||||
Privileged instruction:: No.
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions::
|
|
||||||
MemFault.
|
|
||||||
|
|
||||||
|
|
||||||
<<<
|
<<<
|
||||||
==== Subsystems Instructions
|
==== Subsystems Instructions
|
||||||
===== SSR: Subsystem Register Read
|
include::instructions/ssr.adoc[]
|
||||||
[wavedrom, ,svg]
|
|
||||||
....
|
|
||||||
{reg: [
|
|
||||||
{bits: 7, name: 0x7d, type: 8, attr: '0x7d'},
|
|
||||||
{bits: 5, name: 'reg', type: 2},
|
|
||||||
{bits: 4, name: 'sid', type: 7},
|
|
||||||
{bits: 8, name: 'sre', type: 2},
|
|
||||||
{bits: 8, name: 'cmd', type: 8}
|
|
||||||
], config: {label: {right: 'SSR'}}}
|
|
||||||
....
|
|
||||||
|
|
||||||
Description::
|
|
||||||
Reads a value from a subsystem register into an _Execution Engine_ register.
|
|
||||||
Encoding:: E-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ssr <sid>, <reg>, <sre>, <cmd>
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
sid:::
|
|
||||||
The subsystem identifier.
|
|
||||||
Should be in the range *ss0*..*ss15*.
|
|
||||||
reg::: The _Execution Engine_ destination register.
|
|
||||||
sre:::
|
|
||||||
The subsystem source register.
|
|
||||||
Should be in the range *sr0*..*sr255*.
|
|
||||||
cmd::: The subsystem register specific command to use for reading.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ssr ss0, r1, sr0, 1 <1>
|
|
||||||
ssr ss15, pc, sr32, 0 <2>
|
|
||||||
----
|
|
||||||
<1> Reads the *sr0* register from the *ss0* subsystem into *r1* using the command _0x1_ to do so.
|
|
||||||
<2> Reads the *sr32* register from the *ss15* subsystem into *pc* using the command _0x0_ to do so.
|
|
||||||
|
|
||||||
Privileged instruction:: No. (The access control is done at the register/command level).
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions:: PrivFault.
|
|
||||||
|
|
||||||
<<<
|
<<<
|
||||||
===== SSW: Subsystem Register Write
|
include::instructions/ssw.adoc[]
|
||||||
[wavedrom, ,svg]
|
|
||||||
....
|
|
||||||
{reg: [
|
|
||||||
{bits: 7, name: 0x7e, type: 8, attr: '0x7e'},
|
|
||||||
{bits: 5, name: 'reg', type: 2},
|
|
||||||
{bits: 4, name: 'sid', type: 7},
|
|
||||||
{bits: 8, name: 'sre', type: 2},
|
|
||||||
{bits: 8, name: 'cmd', type: 8}
|
|
||||||
], config: {label: {right: 'SSW'}}}
|
|
||||||
....
|
|
||||||
|
|
||||||
Description::
|
|
||||||
Writes a value from an _Execution Engine_ register into a subsystem register.
|
|
||||||
Encoding:: E-Type
|
|
||||||
Assembler syntax::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ssw <sid>, <reg>, <sre>, <cmd>
|
|
||||||
----
|
|
||||||
+
|
|
||||||
Where:
|
|
||||||
[horizontal]
|
|
||||||
sid:::
|
|
||||||
The subsystem identifier.
|
|
||||||
Should be in the range *ss0*..*ss15*.
|
|
||||||
reg::: The _Execution Engine_ source register.
|
|
||||||
sre:::
|
|
||||||
The subsystem destination register.
|
|
||||||
Should be in the range *sr0*..*sr255*.
|
|
||||||
cmd::: The subsystem register specific command to use for writing.
|
|
||||||
|
|
||||||
Examples::
|
|
||||||
+
|
|
||||||
[source]
|
|
||||||
----
|
|
||||||
ssw ss0, r1, sr0, 1 <1>
|
|
||||||
ssw ss15, pc, sr32, 0 <2>
|
|
||||||
----
|
|
||||||
<1> Writes the value in *r1* into the *sr0* register from the *ss0* subsystem using the command _0x1_ to do so.
|
|
||||||
<2> Writes the value in *pc* into the *sr32* register from the *ss15* subsystem using the command _0x0_ to do so.
|
|
||||||
|
|
||||||
Privileged instruction:: No. (The access control is done at the register/command level).
|
|
||||||
Updates program state flags:: No.
|
|
||||||
Exceptions:: PrivFault.
|
|
||||||
|
|
||||||
|
|||||||
241
src/execution-engine-spec/instructions/b.adoc
Normal file
241
src/execution-engine-spec/instructions/b.adoc
Normal file
@ -0,0 +1,241 @@
|
|||||||
|
===== B: Branch
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0xf, type: 8, attr: '0x0f'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 21, name: 'off', type: 5}
|
||||||
|
], config: {label: {right: 'BIO'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x10, type: 8, attr: '0x10'},
|
||||||
|
{bits: 1, name: 0},
|
||||||
|
{bits: 24, name: 'off', type: 5}
|
||||||
|
], config: {label: {right: 'BAIO'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x11, type: 8, attr: '0x11'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'off[4:0]', type: 5},
|
||||||
|
{bits: 5, name: 'base', type: 4},
|
||||||
|
{bits: 11, name: 'off[15:5]', type: 5}
|
||||||
|
], config: {label: {right: 'BRIA'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x12, type: 8, attr: '0x12'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'unused'},
|
||||||
|
{bits: 5, name: 'base', type: 4},
|
||||||
|
{bits: 5, name: 'off', type: 4},
|
||||||
|
{bits: 6, name: 'unused'}
|
||||||
|
], config: {label: {right: 'BRRA'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x13, type: 8, attr: '0x13'},
|
||||||
|
{bits: 1, name: 0},
|
||||||
|
{bits: 24, name: 'addr', type: 5}
|
||||||
|
], config: {label: {right: 'BAIA'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[frame=ends,grid=rows,cols="1,1"]
|
||||||
|
|===
|
||||||
|
|Instruction variant | Description
|
||||||
|
|
||||||
|
|BIO
|
||||||
|
|<<BIO>>
|
||||||
|
|
||||||
|
|BAIO
|
||||||
|
|<<BAIO>>
|
||||||
|
|
||||||
|
|BRIA
|
||||||
|
|<<BRIA>>
|
||||||
|
|
||||||
|
|BRRA
|
||||||
|
|<<BRRA>>
|
||||||
|
|
||||||
|
|BAIA
|
||||||
|
|<<BAIA>>
|
||||||
|
|===
|
||||||
|
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=BIO]
|
||||||
|
====== BIO: Branch Immediate Offset
|
||||||
|
Description::
|
||||||
|
Branch to the instruction the address of which is at `pc + off`. +
|
||||||
|
The assembler selects this variant over *BAIO* when a condition is given.
|
||||||
|
Encoding:: D1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b<cond> <off>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Condition.
|
||||||
|
off::: Immediate offset.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b.al -20 <1>
|
||||||
|
b.eq 8 <2>
|
||||||
|
----
|
||||||
|
<1> Branches to `pc - 20`.
|
||||||
|
<2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8`. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=BAIO]
|
||||||
|
====== BAIO: Branch Always Immediate Offset
|
||||||
|
Description::
|
||||||
|
Branch to the instruction the address of which is at `pc + off`.
|
||||||
|
Permits the use of more bits for the offset at the cost of being unconditional. +
|
||||||
|
The assembler selects this variant over *BIO* when no condition is given.
|
||||||
|
Encoding:: D2-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b <off>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
off::: Immediate offset.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b -0x3FFFFF <1>
|
||||||
|
----
|
||||||
|
<1> Branches to `pc - 0x3FFFFF`.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=BRIA]
|
||||||
|
====== BRIA: Branch Register+Immediate Absolute
|
||||||
|
Description::
|
||||||
|
Branch to the instruction the address of which is at `base + off`.
|
||||||
|
Permits to use a varying base address with a fixed offset.
|
||||||
|
Encoding:: B2-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b<cond?> [<base>, <off?>]
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
base::: Base register.
|
||||||
|
off:::
|
||||||
|
Optional offset immediate.
|
||||||
|
Must be a multiple of 4 and in the range 0-262140.
|
||||||
|
If omitted, then 0 is used.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b [r0, 12] <1>
|
||||||
|
b.eq [r3] <2>
|
||||||
|
----
|
||||||
|
<1> Branches to the instruction at address `r0 + 12`.
|
||||||
|
<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=BRRA]
|
||||||
|
====== BRRA: Branch Register+Register Absolute
|
||||||
|
Description::
|
||||||
|
Branch to the instruction the address of which is at `base + off`.
|
||||||
|
Permits to use a varying base address with a varying offset.
|
||||||
|
Encoding:: A2-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b<cond?> [<base>, <off>]
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
base::: Base register.
|
||||||
|
off::: Offset register.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b [r0, r1] <1>
|
||||||
|
b.eq [r2, r3] <2>
|
||||||
|
----
|
||||||
|
<1> Branches to the instruction at address `r0 + r1`.
|
||||||
|
<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3`. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=BAIA]
|
||||||
|
====== BAIA: Branch Always Immediate Address
|
||||||
|
Description::
|
||||||
|
Branch to the instruction at the address `addr`.
|
||||||
|
Encoding:: D2-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b <addr>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
addr::: Immediate address.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
b 0x100000 <1>
|
||||||
|
----
|
||||||
|
<1> Branches to the address 0x100000.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
324
src/execution-engine-spec/instructions/ldr.adoc
Normal file
324
src/execution-engine-spec/instructions/ldr.adoc
Normal file
@ -0,0 +1,324 @@
|
|||||||
|
===== LDR: Load Register
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x1, type: 8, attr: '0x01'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 5, name: 'src', type: 4},
|
||||||
|
{bits: 11, name: 'off', type: 5}
|
||||||
|
], config: {label: {right: 'LDRIR'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x2, type: 8, attr: '0x02'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 5, name: 'src', type: 4},
|
||||||
|
{bits: 11, name: 'off', type: 5}
|
||||||
|
], config: {label: {right: 'LDRIRW'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x3, type: 8, attr: '0x03'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 5, name: 'src', type: 4},
|
||||||
|
{bits: 11, name: 'off', type: 5}
|
||||||
|
], config: {label: {right: 'LDRIOW'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x4, type: 8, attr: '0x04'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 5, name: 'src', type: 4},
|
||||||
|
{bits: 5, name: 'off', type: 4},
|
||||||
|
{bits: 6, name: 'unused'}
|
||||||
|
], config: {label: {right: 'LDRR'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x5, type: 8, attr: '0x05'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 5, name: 'src', type: 4},
|
||||||
|
{bits: 5, name: 'off', type: 4},
|
||||||
|
{bits: 6, name: 'unused'}
|
||||||
|
], config: {label: {right: 'LDRRW'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x6, type: 8, attr: '0x06'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 5, name: 'src', type: 4},
|
||||||
|
{bits: 5, name: 'off', type: 4},
|
||||||
|
{bits: 6, name: 'unused'}
|
||||||
|
], config: {label: {right: 'LDROW'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[frame=ends,grid=rows,cols="1,1"]
|
||||||
|
|===
|
||||||
|
|Instruction variant | Description
|
||||||
|
|
||||||
|
|LDRIR
|
||||||
|
|<<LDRIR>>
|
||||||
|
|
||||||
|
|LDRIRW
|
||||||
|
|<<LDRIRW>>
|
||||||
|
|
||||||
|
|LDRIOW
|
||||||
|
|<<LDRIOW>>
|
||||||
|
|
||||||
|
|LDRR
|
||||||
|
|<<LDRR>>
|
||||||
|
|
||||||
|
|LDRRW
|
||||||
|
|<<LDRRW>>
|
||||||
|
|
||||||
|
|LDROW
|
||||||
|
|<<LDROW>>
|
||||||
|
|===
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=LDRIR]
|
||||||
|
====== LDRIR: Load Register+Immediate Pre-indexed
|
||||||
|
Description::
|
||||||
|
Loads a word from memory into a register.
|
||||||
|
The immediate offset `off` is added to the address in the `src` register before reading memory.
|
||||||
|
Encoding:: B1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr<cond?> <dst>, [<src>, <off?>]
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
src::: Source register.
|
||||||
|
off:::
|
||||||
|
Optional offset immediate.
|
||||||
|
Must be a multiple of 4 and in the range 0-8188.
|
||||||
|
If omitted, then 0 is used.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr r1, [r0] <1>
|
||||||
|
ldr r3, [r2, 8] <2>
|
||||||
|
ldr.eq r5, [r4] <3>
|
||||||
|
----
|
||||||
|
<1> Reads a word from the memory address in r0 into r1.
|
||||||
|
<2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3.
|
||||||
|
<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=LDRIRW]
|
||||||
|
====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back
|
||||||
|
Description::
|
||||||
|
Increments the source register then reads a word from memory into the destination register.
|
||||||
|
The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register.
|
||||||
|
Encoding:: B1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr<cond?> <dst>, ![<src>, <off?>]
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
src::: Source register.
|
||||||
|
off:::
|
||||||
|
Optional offset immediate.
|
||||||
|
Must be a multiple of 4 and in the range 0-8188.
|
||||||
|
If omitted, then 4 is used.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr r1, ![r0] <1>
|
||||||
|
ldr r3, ![r2, 8] <2>
|
||||||
|
ldr.eq r5, ![r4] <3>
|
||||||
|
----
|
||||||
|
<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1.
|
||||||
|
<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3.
|
||||||
|
<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=LDRIOW]
|
||||||
|
====== LDRIOW: Load Register+Immediate Post-indexed with Write-back
|
||||||
|
Description::
|
||||||
|
Reads a word from memory into the destination register then increments the source register.
|
||||||
|
The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`.
|
||||||
|
Encoding:: B1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr<cond?> <dst>, [<src>, <off?>]!
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
src::: Source register.
|
||||||
|
off:::
|
||||||
|
Optional offset immediate.
|
||||||
|
Must be a multiple of 4 and in the range 0-8188.
|
||||||
|
If omitted, then 4 is used.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr r1, [r0]! <1>
|
||||||
|
ldr r3, [r2, 8]! <2>
|
||||||
|
ldr.eq r5, [r4]! <3>
|
||||||
|
----
|
||||||
|
<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4.
|
||||||
|
<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8.
|
||||||
|
<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=LDRR]
|
||||||
|
====== LDRR: Load Register+Register Pre-indexed
|
||||||
|
Description::
|
||||||
|
Loads a word from memory into a register.
|
||||||
|
The value in the register `off` is added to the address in the `src` register before reading memory.
|
||||||
|
Encoding:: A1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr<cond?> <dst>, [<src>, <off>]
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
src::: Source register.
|
||||||
|
off::: Offset register.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr r1, [sp, r0] <1>
|
||||||
|
ldr.eq r0, [r1, r2] <2>
|
||||||
|
----
|
||||||
|
<1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset.
|
||||||
|
<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=LDRRW]
|
||||||
|
====== LDRRW: Load Register+Register Pre-indexed with Write-back
|
||||||
|
Description::
|
||||||
|
Increments the source register then reads a word from memory into the destination register.
|
||||||
|
The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register.
|
||||||
|
Encoding:: A1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr<cond?> <dst>, ![<src>, <off>]
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
src::: Source register.
|
||||||
|
off::: Offset register.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr r1, ![sp, r0] <1>
|
||||||
|
ldr.eq r0, ![r1, r2] <2>
|
||||||
|
----
|
||||||
|
<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1.
|
||||||
|
<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=LDROW]
|
||||||
|
====== LDROW: Load Register+Register Post-indexed with Write-back
|
||||||
|
Description::
|
||||||
|
Reads a word from memory into the destination register then increments the source register.
|
||||||
|
The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`.
|
||||||
|
Encoding:: A1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr<cond?> <dst>, [<src>, <off>]!
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
src::: Source register.
|
||||||
|
off::: Offset register.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ldr r1, [sp, r0]! <1>
|
||||||
|
ldr.eq r0, [r1, r2]! <2>
|
||||||
|
----
|
||||||
|
<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp.
|
||||||
|
<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
101
src/execution-engine-spec/instructions/mov.adoc
Normal file
101
src/execution-engine-spec/instructions/mov.adoc
Normal file
@ -0,0 +1,101 @@
|
|||||||
|
===== MOV: Move to Register
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0xd, type: 8, attr: '0x0d'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 5, name: 'src', type: 4},
|
||||||
|
{bits: 11, name: 'unused'}
|
||||||
|
], config: {label: {right: 'MOVR'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0xe, type: 8, attr: '0x0e'},
|
||||||
|
{bits: 4, name: 'cond', type: 6},
|
||||||
|
{bits: 5, name: 'dst', type: 2},
|
||||||
|
{bits: 16, name: 'val', type: 5}
|
||||||
|
], config: {label: {right: 'MOVI'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
[frame=ends,grid=rows,cols="1,1"]
|
||||||
|
|===
|
||||||
|
|Instruction variant | Description
|
||||||
|
|
||||||
|
|MOVR
|
||||||
|
|<<MOVR>>
|
||||||
|
|
||||||
|
|MOVI
|
||||||
|
|<<MOVI>>
|
||||||
|
|===
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=MOVR]
|
||||||
|
====== MOVR: Move Register to Register
|
||||||
|
Description::
|
||||||
|
Copies the value of a source register into a destination register.
|
||||||
|
Encoding:: B1-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
mov<cond?> <dst>, <src>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
src::: Source register.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
mov r1, r0 <1>
|
||||||
|
mov.lt r3, lr <2>
|
||||||
|
----
|
||||||
|
<1> Copies the value from r0 into r1.
|
||||||
|
<2> If the last comparison resulted in an 'lt' condition status, copies the value from lr into r3. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
None.
|
||||||
|
|
||||||
|
<<<
|
||||||
|
[id=MOVI]
|
||||||
|
====== MOVI: Move Immediate to Register
|
||||||
|
Description::
|
||||||
|
Sets a destination register to the value given in the immediate field.
|
||||||
|
Encoding:: C-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
mov<cond?> <dst>, <val>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
cond::: Optional condition.
|
||||||
|
dst::: Destination register.
|
||||||
|
val::: Immediate value.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
mov r0, 42 <1>
|
||||||
|
mov.eq r1, 1337 <2>
|
||||||
|
----
|
||||||
|
<1> Sets r0 to 42.
|
||||||
|
<2> If the last comparison resulted in an 'eq' condition status, sets r1 to 1337. Else, does nothing.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
None.
|
||||||
|
|
||||||
22
src/execution-engine-spec/instructions/nop.adoc
Normal file
22
src/execution-engine-spec/instructions/nop.adoc
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
===== NOP: No Operation
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x0, type: 8, attr: '0x00'},
|
||||||
|
{bits: 25, name: 'unused'}
|
||||||
|
], config: {label: {right: 'NOP'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
Description::
|
||||||
|
Does nothing. Can be used to align a block of instructions.
|
||||||
|
Encoding:: D2-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
nop
|
||||||
|
----
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions:: None.
|
||||||
|
|
||||||
47
src/execution-engine-spec/instructions/ssr.adoc
Normal file
47
src/execution-engine-spec/instructions/ssr.adoc
Normal file
@ -0,0 +1,47 @@
|
|||||||
|
===== SSR: Subsystem Register Read
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x7d, type: 8, attr: '0x7d'},
|
||||||
|
{bits: 5, name: 'reg', type: 2},
|
||||||
|
{bits: 4, name: 'sid', type: 7},
|
||||||
|
{bits: 8, name: 'sre', type: 2},
|
||||||
|
{bits: 8, name: 'cmd', type: 8}
|
||||||
|
], config: {label: {right: 'SSR'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
Description::
|
||||||
|
Reads a value from a subsystem register into an _Execution Engine_ register.
|
||||||
|
Encoding:: E-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ssr <sid>, <reg>, <sre>, <cmd>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
sid:::
|
||||||
|
The subsystem identifier.
|
||||||
|
Should be in the range *ss0*..*ss15*.
|
||||||
|
reg::: The _Execution Engine_ destination register.
|
||||||
|
sre:::
|
||||||
|
The subsystem source register.
|
||||||
|
Should be in the range *sr0*..*sr255*.
|
||||||
|
cmd::: The subsystem register specific command to use for reading.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ssr ss0, r1, sr0, 1 <1>
|
||||||
|
ssr ss15, pc, sr32, 0 <2>
|
||||||
|
----
|
||||||
|
<1> Reads the sr0 register from the ss0 subsystem into r1 using the command _0x1_ to do so.
|
||||||
|
<2> Reads the sr32 register from the ss15 subsystem into pc using the command _0x0_ to do so.
|
||||||
|
|
||||||
|
Privileged instruction:: No. (The access control is done at the register/command level).
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions:: PrivFault.
|
||||||
|
|
||||||
47
src/execution-engine-spec/instructions/ssw.adoc
Normal file
47
src/execution-engine-spec/instructions/ssw.adoc
Normal file
@ -0,0 +1,47 @@
|
|||||||
|
===== SSW: Subsystem Register Write
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x7e, type: 8, attr: '0x7e'},
|
||||||
|
{bits: 5, name: 'reg', type: 2},
|
||||||
|
{bits: 4, name: 'sid', type: 7},
|
||||||
|
{bits: 8, name: 'sre', type: 2},
|
||||||
|
{bits: 8, name: 'cmd', type: 8}
|
||||||
|
], config: {label: {right: 'SSW'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
Description::
|
||||||
|
Writes a value from an _Execution Engine_ register into a subsystem register.
|
||||||
|
Encoding:: E-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ssw <sid>, <reg>, <sre>, <cmd>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
sid:::
|
||||||
|
The subsystem identifier.
|
||||||
|
Should be in the range *ss0*..*ss15*.
|
||||||
|
reg::: The _Execution Engine_ source register.
|
||||||
|
sre:::
|
||||||
|
The subsystem destination register.
|
||||||
|
Should be in the range *sr0*..*sr255*.
|
||||||
|
cmd::: The subsystem register specific command to use for writing.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
ssw ss0, r1, sr0, 1 <1>
|
||||||
|
ssw ss15, pc, sr32, 0 <2>
|
||||||
|
----
|
||||||
|
<1> Writes the value in r1 into the sr0 register from the ss0 subsystem using the command _0x1_ to do so.
|
||||||
|
<2> Writes the value in pc into the sr32 register from the ss15 subsystem using the command _0x0_ to do so.
|
||||||
|
|
||||||
|
Privileged instruction:: No. (The access control is done at the register/command level).
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions:: PrivFault.
|
||||||
|
|
||||||
38
src/execution-engine-spec/instructions/svc.adoc
Normal file
38
src/execution-engine-spec/instructions/svc.adoc
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
===== SVC: Supervisor Call
|
||||||
|
[wavedrom, ,svg]
|
||||||
|
....
|
||||||
|
{reg: [
|
||||||
|
{bits: 7, name: 0x7f, type: 8, attr: '0x7e'},
|
||||||
|
{bits: 25, name: 'svc_num', type: 5}
|
||||||
|
], config: {label: {right: 'SVC'}}}
|
||||||
|
....
|
||||||
|
|
||||||
|
Description::
|
||||||
|
Generates an SVC exception to execute a privileged operation.
|
||||||
|
Encoding:: D2-Type
|
||||||
|
Assembler syntax::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
svc <svc_num>
|
||||||
|
----
|
||||||
|
+
|
||||||
|
Where:
|
||||||
|
[horizontal]
|
||||||
|
svc_num:::
|
||||||
|
An immediate number identifying the privileged operation to execute.
|
||||||
|
|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
svc 128 <1>
|
||||||
|
svc 0xff <2>
|
||||||
|
----
|
||||||
|
<1> Calls the privileged operation number 128 that is exposed by the kernel.
|
||||||
|
<2> Calls the privileged operation number 255 that is exposed by the kernel.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions:: SVC.
|
||||||
|
|
||||||
@ -30,7 +30,7 @@ The {central-arch-name} allows up to 16 subystem identifiers. Not all of these i
|
|||||||
|#TODO: Describe it.#
|
|#TODO: Describe it.#
|
||||||
|===
|
|===
|
||||||
|
|
||||||
|
<<<
|
||||||
[id=debugging-subsystem]
|
[id=debugging-subsystem]
|
||||||
=== Debugging Subsystem
|
=== Debugging Subsystem
|
||||||
==== Description
|
==== Description
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user