From 955251bea68ff2b7bed185accfde6ac189595506 Mon Sep 17 00:00:00 2001 From: Elyan Date: Sat, 2 Nov 2024 00:44:24 +0100 Subject: [PATCH] Split the instructions in multiple files and added move and branch instructions --- .../images/instruction-formats.adoc | 60 -- .../instruction-formats.adoc | 115 ++++ src/execution-engine-spec/instructions.adoc | 523 +----------------- src/execution-engine-spec/instructions/b.adoc | 241 ++++++++ .../instructions/ldr.adoc | 324 +++++++++++ .../instructions/mov.adoc | 101 ++++ .../instructions/nop.adoc | 22 + .../instructions/ssr.adoc | 47 ++ .../instructions/ssw.adoc | 47 ++ .../instructions/svc.adoc | 38 ++ src/execution-engine-spec/subsystems.adoc | 2 +- 11 files changed, 949 insertions(+), 571 deletions(-) delete mode 100644 src/execution-engine-spec/images/instruction-formats.adoc create mode 100644 src/execution-engine-spec/instruction-formats.adoc create mode 100644 src/execution-engine-spec/instructions/b.adoc create mode 100644 src/execution-engine-spec/instructions/ldr.adoc create mode 100644 src/execution-engine-spec/instructions/mov.adoc create mode 100644 src/execution-engine-spec/instructions/nop.adoc create mode 100644 src/execution-engine-spec/instructions/ssr.adoc create mode 100644 src/execution-engine-spec/instructions/ssw.adoc create mode 100644 src/execution-engine-spec/instructions/svc.adoc diff --git a/src/execution-engine-spec/images/instruction-formats.adoc b/src/execution-engine-spec/images/instruction-formats.adoc deleted file mode 100644 index 85769a7..0000000 --- a/src/execution-engine-spec/images/instruction-formats.adoc +++ /dev/null @@ -1,60 +0,0 @@ -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'rd', type: 2}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 5, name: 'rs2', type: 4}, - {bits: 6, name: 'imm', type: 5} -], config: {label: {right: 'A-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'rd', type: 2}, - {bits: 5, name: 'rs1', type: 4}, - {bits: 11, name: 'imm', type: 5} -], config: {label: {right: 'B-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'rd', type: 2}, - {bits: 16, name: 'imm', type: 5} -], config: {label: {right: 'C-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 4, name: 'cond', type: 6}, - {bits: 21, name: 'imm', type: 5} -], config: {label: {right: 'D1-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 25, name: 'imm', type: 5} -], config: {label: {right: 'D2-Type'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 'opcode', type: 8}, - {bits: 5, name: 'reg', type: 2}, - {bits: 4, name: 'sid', type: 7}, - {bits: 8, name: 'sre', type: 2}, - {bits: 8, name: 'cmd', type: 8} -], config: {label: {right: 'E-Type'}}} -.... \ No newline at end of file diff --git a/src/execution-engine-spec/instruction-formats.adoc b/src/execution-engine-spec/instruction-formats.adoc new file mode 100644 index 0000000..e40c417 --- /dev/null +++ b/src/execution-engine-spec/instruction-formats.adoc @@ -0,0 +1,115 @@ +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'rd', type: 2}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 5, name: 'rs2', type: 4}, + {bits: 6, name: 'imm', type: 5} +], config: {label: {right: 'A1-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'imm[4:0]', type: 5}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 5, name: 'rs2', type: 4}, + {bits: 6, name: 'imm[10:5]', type: 5} +], config: {label: {right: 'A2-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'rd', type: 2}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 11, name: 'imm', type: 5} +], config: {label: {right: 'B1-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'imm[4:0]', type: 5}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 11, name: 'imm[15:5]', type: 5} +], config: {label: {right: 'B2-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'rd', type: 2}, + {bits: 16, name: 'imm', type: 5} +], config: {label: {right: 'C-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 21, name: 'imm', type: 5} +], config: {label: {right: 'D1-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 1, name: 0}, + {bits: 24, name: 'imm', type: 5} +], config: {label: {right: 'D2-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 5, name: 'reg', type: 2}, + {bits: 4, name: 'sid', type: 7}, + {bits: 8, name: 'sre', type: 2}, + {bits: 8, name: 'cmd', type: 8} +], config: {label: {right: 'E-Type'}}} +.... + +.Format fields +[horizontal] +opcode:: + The operation to carry on. +cond:: + Condition code. + + See <>. +rd:: + Destination register. + + See <>. +rs1:: + Source register 1. +rs2:: + Source register 2. +imm:: + Immediate value. + + Can be interpreted as signed or unsigned depending on the instruction. +reg:: + Source/destination register on the _Execution Engine_ side. + + See <>. +sid:: + Subsystem ID. + + See <>. +sre:: + Source/destination register on the subsystem side. + + See <>. +cmd:: + Subsystem register command. + + Specific to the accessed subsystem register. More info in <>. + diff --git a/src/execution-engine-spec/instructions.adoc b/src/execution-engine-spec/instructions.adoc index 3bf6b3f..b65f844 100644 --- a/src/execution-engine-spec/instructions.adoc +++ b/src/execution-engine-spec/instructions.adoc @@ -6,538 +6,41 @@ The source (rs1 and rs2) and destination (rd) registers are kept at the same pos For instruction encoding formats that contain an immediate value, not all immediate bits are used by all instructions sharing the format. The actual relevant bits are specified for these instructions. -include::images/instruction-formats.adoc[] - -.Format fields -[horizontal] -opcode:: - The operation to carry on. -cond:: - Condition code. + - See <>. -rd:: - Destination register. + - See <>. -rs1:: - Source register 1. -rs2:: - Source register 2. -imm:: - Immediate value. + - Can be interpreted as signed or unsigned depending on the instruction. -reg:: - Source/destination register on the _Execution Engine_ side. + - See <>. -sid:: - Subsystem ID. + - See <>. -sre:: - Source/destination register on the subsystem side. + - See <>. -cmd:: - Subsystem register command. + - Specific to the accessed subsystem register. More info in <>. - +include::instruction-formats.adoc[] +<<< include::instructions-operands-encoding.adoc[] <<< === Instruction List #TODO: List instructions# -* NOP instruction * memory load/store instructions -* register move instructions * arithmetic instructions * bitwise operations instructions (w/ bit shifts) * comparison instructions * jump instructions * system mode instructions (svc, uret, sret, ...) -* subsystems instructions (ssr & ssw) ==== Miscellaneous Instructions -===== NOP: No Operation -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x0, type: 8, attr: '0x0'}, - {bits: 25, name: 'unused'} -], config: {label: {right: 'NOP'}}} -.... - -Description:: - Does nothing. Can be used to align a block of instructions. -Encoding:: D2-Type -Assembler syntax:: -+ -[source] ----- -nop ----- -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: None. +include::instructions/nop.adoc[] +<<< +include::instructions/svc.adoc[] <<< -===== SVC: Supervisor Call -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x7f, type: 8, attr: '0x7e'}, - {bits: 25, name: 'svc_num', type: 5} -], config: {label: {right: 'SVC'}}} -.... - -Description:: - Generates an SVC exception to execute a privileged operation. -Encoding:: D2-Type -Assembler syntax:: -+ -[source] ----- -svc ----- -+ -Where: -[horizontal] -svc_num::: - A constant identifying the privileged operation to execute. + - Must be in the range 0..33554431 (0x0..0x1FFFFFF). - -Examples:: -+ -[source] ----- -svc 128 <1> -svc 0xff <2> ----- -<1> Calls the privileged operation number 128 that is exposed by the kernel. -<2> Calls the privileged operation number 255 that is exposed by the kernel. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: SVC. +==== Memory-Related Instructions +include::instructions/ldr.adoc[] <<< -==== Memory-related instructions -===== LDR: Load Register -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x1, type: 8, attr: '0x1'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 11, name: 'off', type: 5} -], config: {label: {right: 'LDRIR'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x2, type: 8, attr: '0x2'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 11, name: 'off', type: 5} -], config: {label: {right: 'LDRIRW'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x3, type: 8, attr: '0x3'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 11, name: 'off', type: 5} -], config: {label: {right: 'LDRIOW'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x4, type: 8, attr: '0x4'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 5, name: 'off', type: 4}, - {bits: 6, name: 'unused'} -], config: {label: {right: 'LDRR'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x5, type: 8, attr: '0x5'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 5, name: 'off', type: 4}, - {bits: 6, name: 'unused'} -], config: {label: {right: 'LDRRW'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x6, type: 8, attr: '0x6'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 5, name: 'off', type: 4}, - {bits: 6, name: 'unused'} -], config: {label: {right: 'LDROW'}}} -.... - -[frame=ends,grid=rows,cols="1,1"] -|=== -|Instruction variant | Description - -|LDRIR -|<> - -|LDRIRW -|<> - -|LDRIOW -|<> - -|LDRR -|<> - -|LDRRW -|<> - -|LDROW -|<> -|=== +==== Register Manipulation Instructions +include::instructions/mov.adoc[] <<< -[id=LDRIR] -====== LDRIR: Load Register+Immediate Pre-indexed -Description:: - Loads a word from memory into a register. - The immediate offset `off` is added to the address in the `src` register before reading memory. -Encoding:: A-Type -Assembler syntax:: -+ -[source] ----- -ldr , [, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: - Optional offset immediate. - Must be a multiple of 4 and in the range 0-8188. - If omitted, then 0 is used. - -Examples:: -+ -[source] ----- -ldr r1, [r0] <1> -ldr r3, [r2, 8] <2> -ldr.eq r5, [r4] <3> ----- -<1> Reads a word from the memory address in r0 into r1. -<2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3. -<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDRIRW] -====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back -Description:: - Increments the source register then reads a word from memory into the destination register. - The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register. -Encoding:: A-Type -Assembler syntax:: -+ -[source] ----- -ldr , ![, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: - Optional offset immediate. - Must be a multiple of 4 and in the range 0-8188. - If omitted, then 4 is used. - -Examples:: -+ -[source] ----- -ldr r1, ![r0] <1> -ldr r3, ![r2, 8] <2> -ldr.eq r5, ![r4] <3> ----- -<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1. -<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3. -<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDRIOW] -====== LDRIOW: Load Register+Immediate Post-indexed with Write-back -Description:: - Reads a word from memory into the destination register then increments the source register. - The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`. -Encoding:: A-Type -Assembler syntax:: -+ -[source] ----- -ldr , [, ]! ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: - Optional offset immediate. - Must be a multiple of 4 and in the range 0-8188. - If omitted, then 4 is used. - -Examples:: -+ -[source] ----- -ldr r1, [r0]! <1> -ldr r3, [r2, 8]! <2> -ldr.eq r5, [r4]! <3> ----- -<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4. -<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8. -<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDRR] -====== LDRR: Load Register+Register Pre-indexed -Description:: - Loads a word from memory into a register. - The value in the register `off` is added to the address in the `src` register before reading memory. -Encoding:: A-Type -Assembler syntax:: -+ -[source] ----- -ldr , [, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: Offset register. - -Examples:: -+ -[source] ----- -ldr r1, [sp, r0] <1> -ldr.eq r0, [r1, r2] <2> ----- -<1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset. -<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDRRW] -====== LDRRW: Load Register+Register Pre-indexed with Write-back -Description:: - Increments the source register then reads a word from memory into the destination register. - The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register. -Encoding:: A-Type -Assembler syntax:: -+ -[source] ----- -ldr , ![, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: Offset register. - -Examples:: -+ -[source] ----- -ldr r1, ![sp, r0] <1> -ldr.eq r0, ![r1, r2] <2> ----- -<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1. -<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDROW] -====== LDROW: Load Register+Register Post-indexed with Write-back -Description:: - Reads a word from memory into the destination register then increments the source register. - The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`. -Encoding:: A-Type -Assembler syntax:: -+ -[source] ----- -ldr , [, ]! ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: Offset register. - -Examples:: -+ -[source] ----- -ldr r1, [sp, r0]! <1> -ldr.eq r0, [r1, r2]! <2> ----- -<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp. -<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - +==== Branching Instructions +include::instructions/b.adoc[] <<< ==== Subsystems Instructions -===== SSR: Subsystem Register Read -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x7d, type: 8, attr: '0x7d'}, - {bits: 5, name: 'reg', type: 2}, - {bits: 4, name: 'sid', type: 7}, - {bits: 8, name: 'sre', type: 2}, - {bits: 8, name: 'cmd', type: 8} -], config: {label: {right: 'SSR'}}} -.... - -Description:: - Reads a value from a subsystem register into an _Execution Engine_ register. -Encoding:: E-Type -Assembler syntax:: -+ -[source] ----- -ssr , , , ----- -+ -Where: -[horizontal] -sid::: - The subsystem identifier. - Should be in the range *ss0*..*ss15*. -reg::: The _Execution Engine_ destination register. -sre::: - The subsystem source register. - Should be in the range *sr0*..*sr255*. -cmd::: The subsystem register specific command to use for reading. - -Examples:: -+ -[source] ----- -ssr ss0, r1, sr0, 1 <1> -ssr ss15, pc, sr32, 0 <2> ----- -<1> Reads the *sr0* register from the *ss0* subsystem into *r1* using the command _0x1_ to do so. -<2> Reads the *sr32* register from the *ss15* subsystem into *pc* using the command _0x0_ to do so. - -Privileged instruction:: No. (The access control is done at the register/command level). -Updates program state flags:: No. -Exceptions:: PrivFault. - +include::instructions/ssr.adoc[] <<< -===== SSW: Subsystem Register Write -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x7e, type: 8, attr: '0x7e'}, - {bits: 5, name: 'reg', type: 2}, - {bits: 4, name: 'sid', type: 7}, - {bits: 8, name: 'sre', type: 2}, - {bits: 8, name: 'cmd', type: 8} -], config: {label: {right: 'SSW'}}} -.... - -Description:: - Writes a value from an _Execution Engine_ register into a subsystem register. -Encoding:: E-Type -Assembler syntax:: -+ -[source] ----- -ssw , , , ----- -+ -Where: -[horizontal] -sid::: - The subsystem identifier. - Should be in the range *ss0*..*ss15*. -reg::: The _Execution Engine_ source register. -sre::: - The subsystem destination register. - Should be in the range *sr0*..*sr255*. -cmd::: The subsystem register specific command to use for writing. - -Examples:: -+ -[source] ----- -ssw ss0, r1, sr0, 1 <1> -ssw ss15, pc, sr32, 0 <2> ----- -<1> Writes the value in *r1* into the *sr0* register from the *ss0* subsystem using the command _0x1_ to do so. -<2> Writes the value in *pc* into the *sr32* register from the *ss15* subsystem using the command _0x0_ to do so. - -Privileged instruction:: No. (The access control is done at the register/command level). -Updates program state flags:: No. -Exceptions:: PrivFault. +include::instructions/ssw.adoc[] diff --git a/src/execution-engine-spec/instructions/b.adoc b/src/execution-engine-spec/instructions/b.adoc new file mode 100644 index 0000000..6f4b169 --- /dev/null +++ b/src/execution-engine-spec/instructions/b.adoc @@ -0,0 +1,241 @@ +===== B: Branch +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0xf, type: 8, attr: '0x0f'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 21, name: 'off', type: 5} +], config: {label: {right: 'BIO'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x10, type: 8, attr: '0x10'}, + {bits: 1, name: 0}, + {bits: 24, name: 'off', type: 5} +], config: {label: {right: 'BAIO'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x11, type: 8, attr: '0x11'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'off[4:0]', type: 5}, + {bits: 5, name: 'base', type: 4}, + {bits: 11, name: 'off[15:5]', type: 5} +], config: {label: {right: 'BRIA'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x12, type: 8, attr: '0x12'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'unused'}, + {bits: 5, name: 'base', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'BRRA'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x13, type: 8, attr: '0x13'}, + {bits: 1, name: 0}, + {bits: 24, name: 'addr', type: 5} +], config: {label: {right: 'BAIA'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|BIO +|<> + +|BAIO +|<> + +|BRIA +|<> + +|BRRA +|<> + +|BAIA +|<> +|=== + + +<<< +[id=BIO] +====== BIO: Branch Immediate Offset +Description:: + Branch to the instruction the address of which is at `pc + off`. + + The assembler selects this variant over *BAIO* when a condition is given. +Encoding:: D1-Type +Assembler syntax:: ++ +[source] +---- +b +---- ++ +Where: +[horizontal] +cond::: Condition. +off::: Immediate offset. + +Examples:: ++ +[source] +---- +b.al -20 <1> +b.eq 8 <2> +---- +<1> Branches to `pc - 20`. +<2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8`. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=BAIO] +====== BAIO: Branch Always Immediate Offset +Description:: + Branch to the instruction the address of which is at `pc + off`. + Permits the use of more bits for the offset at the cost of being unconditional. + + The assembler selects this variant over *BIO* when no condition is given. +Encoding:: D2-Type +Assembler syntax:: ++ +[source] +---- +b +---- ++ +Where: +[horizontal] +off::: Immediate offset. + +Examples:: ++ +[source] +---- +b -0x3FFFFF <1> +---- +<1> Branches to `pc - 0x3FFFFF`. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=BRIA] +====== BRIA: Branch Register+Immediate Absolute +Description:: + Branch to the instruction the address of which is at `base + off`. + Permits to use a varying base address with a fixed offset. +Encoding:: B2-Type +Assembler syntax:: ++ +[source] +---- +b [, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +base::: Base register. +off::: + Optional offset immediate. + Must be a multiple of 4 and in the range 0-262140. + If omitted, then 0 is used. + +Examples:: ++ +[source] +---- +b [r0, 12] <1> +b.eq [r3] <2> +---- +<1> Branches to the instruction at address `r0 + 12`. +<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=BRRA] +====== BRRA: Branch Register+Register Absolute +Description:: + Branch to the instruction the address of which is at `base + off`. + Permits to use a varying base address with a varying offset. +Encoding:: A2-Type +Assembler syntax:: ++ +[source] +---- +b [, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +base::: Base register. +off::: Offset register. + +Examples:: ++ +[source] +---- +b [r0, r1] <1> +b.eq [r2, r3] <2> +---- +<1> Branches to the instruction at address `r0 + r1`. +<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3`. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=BAIA] +====== BAIA: Branch Always Immediate Address +Description:: + Branch to the instruction at the address `addr`. +Encoding:: D2-Type +Assembler syntax:: ++ +[source] +---- +b +---- ++ +Where: +[horizontal] +addr::: Immediate address. + +Examples:: ++ +[source] +---- +b 0x100000 <1> +---- +<1> Branches to the address 0x100000. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + diff --git a/src/execution-engine-spec/instructions/ldr.adoc b/src/execution-engine-spec/instructions/ldr.adoc new file mode 100644 index 0000000..9669e40 --- /dev/null +++ b/src/execution-engine-spec/instructions/ldr.adoc @@ -0,0 +1,324 @@ +===== LDR: Load Register +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x1, type: 8, attr: '0x01'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off', type: 5} +], config: {label: {right: 'LDRIR'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x2, type: 8, attr: '0x02'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off', type: 5} +], config: {label: {right: 'LDRIRW'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x3, type: 8, attr: '0x03'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off', type: 5} +], config: {label: {right: 'LDRIOW'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x4, type: 8, attr: '0x04'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDRR'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x5, type: 8, attr: '0x05'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDRRW'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x6, type: 8, attr: '0x06'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDROW'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|LDRIR +|<> + +|LDRIRW +|<> + +|LDRIOW +|<> + +|LDRR +|<> + +|LDRRW +|<> + +|LDROW +|<> +|=== + +<<< +[id=LDRIR] +====== LDRIR: Load Register+Immediate Pre-indexed +Description:: + Loads a word from memory into a register. + The immediate offset `off` is added to the address in the `src` register before reading memory. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +ldr , [, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +src::: Source register. +off::: + Optional offset immediate. + Must be a multiple of 4 and in the range 0-8188. + If omitted, then 0 is used. + +Examples:: ++ +[source] +---- +ldr r1, [r0] <1> +ldr r3, [r2, 8] <2> +ldr.eq r5, [r4] <3> +---- +<1> Reads a word from the memory address in r0 into r1. +<2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3. +<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=LDRIRW] +====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back +Description:: + Increments the source register then reads a word from memory into the destination register. + The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +ldr , ![, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +src::: Source register. +off::: + Optional offset immediate. + Must be a multiple of 4 and in the range 0-8188. + If omitted, then 4 is used. + +Examples:: ++ +[source] +---- +ldr r1, ![r0] <1> +ldr r3, ![r2, 8] <2> +ldr.eq r5, ![r4] <3> +---- +<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1. +<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3. +<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=LDRIOW] +====== LDRIOW: Load Register+Immediate Post-indexed with Write-back +Description:: + Reads a word from memory into the destination register then increments the source register. + The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +ldr , [, ]! +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +src::: Source register. +off::: + Optional offset immediate. + Must be a multiple of 4 and in the range 0-8188. + If omitted, then 4 is used. + +Examples:: ++ +[source] +---- +ldr r1, [r0]! <1> +ldr r3, [r2, 8]! <2> +ldr.eq r5, [r4]! <3> +---- +<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4. +<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8. +<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=LDRR] +====== LDRR: Load Register+Register Pre-indexed +Description:: + Loads a word from memory into a register. + The value in the register `off` is added to the address in the `src` register before reading memory. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +ldr , [, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +src::: Source register. +off::: Offset register. + +Examples:: ++ +[source] +---- +ldr r1, [sp, r0] <1> +ldr.eq r0, [r1, r2] <2> +---- +<1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset. +<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=LDRRW] +====== LDRRW: Load Register+Register Pre-indexed with Write-back +Description:: + Increments the source register then reads a word from memory into the destination register. + The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +ldr , ![, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +src::: Source register. +off::: Offset register. + +Examples:: ++ +[source] +---- +ldr r1, ![sp, r0] <1> +ldr.eq r0, ![r1, r2] <2> +---- +<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1. +<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=LDROW] +====== LDROW: Load Register+Register Post-indexed with Write-back +Description:: + Reads a word from memory into the destination register then increments the source register. + The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +ldr , [, ]! +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +src::: Source register. +off::: Offset register. + +Examples:: ++ +[source] +---- +ldr r1, [sp, r0]! <1> +ldr.eq r0, [r1, r2]! <2> +---- +<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp. +<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + diff --git a/src/execution-engine-spec/instructions/mov.adoc b/src/execution-engine-spec/instructions/mov.adoc new file mode 100644 index 0000000..6f49682 --- /dev/null +++ b/src/execution-engine-spec/instructions/mov.adoc @@ -0,0 +1,101 @@ +===== MOV: Move to Register +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0xd, type: 8, attr: '0x0d'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'unused'} +], config: {label: {right: 'MOVR'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0xe, type: 8, attr: '0x0e'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 16, name: 'val', type: 5} +], config: {label: {right: 'MOVI'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|MOVR +|<> + +|MOVI +|<> +|=== + +<<< +[id=MOVR] +====== MOVR: Move Register to Register +Description:: + Copies the value of a source register into a destination register. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +mov , +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +src::: Source register. + +Examples:: ++ +[source] +---- +mov r1, r0 <1> +mov.lt r3, lr <2> +---- +<1> Copies the value from r0 into r1. +<2> If the last comparison resulted in an 'lt' condition status, copies the value from lr into r3. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + None. + +<<< +[id=MOVI] +====== MOVI: Move Immediate to Register +Description:: + Sets a destination register to the value given in the immediate field. +Encoding:: C-Type +Assembler syntax:: ++ +[source] +---- +mov , +---- ++ +Where: +[horizontal] +cond::: Optional condition. +dst::: Destination register. +val::: Immediate value. + +Examples:: ++ +[source] +---- +mov r0, 42 <1> +mov.eq r1, 1337 <2> +---- +<1> Sets r0 to 42. +<2> If the last comparison resulted in an 'eq' condition status, sets r1 to 1337. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + None. + diff --git a/src/execution-engine-spec/instructions/nop.adoc b/src/execution-engine-spec/instructions/nop.adoc new file mode 100644 index 0000000..0ce2707 --- /dev/null +++ b/src/execution-engine-spec/instructions/nop.adoc @@ -0,0 +1,22 @@ +===== NOP: No Operation +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x0, type: 8, attr: '0x00'}, + {bits: 25, name: 'unused'} +], config: {label: {right: 'NOP'}}} +.... + +Description:: + Does nothing. Can be used to align a block of instructions. +Encoding:: D2-Type +Assembler syntax:: ++ +[source] +---- +nop +---- +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: None. + diff --git a/src/execution-engine-spec/instructions/ssr.adoc b/src/execution-engine-spec/instructions/ssr.adoc new file mode 100644 index 0000000..7d75f4d --- /dev/null +++ b/src/execution-engine-spec/instructions/ssr.adoc @@ -0,0 +1,47 @@ +===== SSR: Subsystem Register Read +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x7d, type: 8, attr: '0x7d'}, + {bits: 5, name: 'reg', type: 2}, + {bits: 4, name: 'sid', type: 7}, + {bits: 8, name: 'sre', type: 2}, + {bits: 8, name: 'cmd', type: 8} +], config: {label: {right: 'SSR'}}} +.... + +Description:: + Reads a value from a subsystem register into an _Execution Engine_ register. +Encoding:: E-Type +Assembler syntax:: ++ +[source] +---- +ssr , , , +---- ++ +Where: +[horizontal] +sid::: + The subsystem identifier. + Should be in the range *ss0*..*ss15*. +reg::: The _Execution Engine_ destination register. +sre::: + The subsystem source register. + Should be in the range *sr0*..*sr255*. +cmd::: The subsystem register specific command to use for reading. + +Examples:: ++ +[source] +---- +ssr ss0, r1, sr0, 1 <1> +ssr ss15, pc, sr32, 0 <2> +---- +<1> Reads the sr0 register from the ss0 subsystem into r1 using the command _0x1_ to do so. +<2> Reads the sr32 register from the ss15 subsystem into pc using the command _0x0_ to do so. + +Privileged instruction:: No. (The access control is done at the register/command level). +Updates program state flags:: No. +Exceptions:: PrivFault. + diff --git a/src/execution-engine-spec/instructions/ssw.adoc b/src/execution-engine-spec/instructions/ssw.adoc new file mode 100644 index 0000000..f076112 --- /dev/null +++ b/src/execution-engine-spec/instructions/ssw.adoc @@ -0,0 +1,47 @@ +===== SSW: Subsystem Register Write +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x7e, type: 8, attr: '0x7e'}, + {bits: 5, name: 'reg', type: 2}, + {bits: 4, name: 'sid', type: 7}, + {bits: 8, name: 'sre', type: 2}, + {bits: 8, name: 'cmd', type: 8} +], config: {label: {right: 'SSW'}}} +.... + +Description:: + Writes a value from an _Execution Engine_ register into a subsystem register. +Encoding:: E-Type +Assembler syntax:: ++ +[source] +---- +ssw , , , +---- ++ +Where: +[horizontal] +sid::: + The subsystem identifier. + Should be in the range *ss0*..*ss15*. +reg::: The _Execution Engine_ source register. +sre::: + The subsystem destination register. + Should be in the range *sr0*..*sr255*. +cmd::: The subsystem register specific command to use for writing. + +Examples:: ++ +[source] +---- +ssw ss0, r1, sr0, 1 <1> +ssw ss15, pc, sr32, 0 <2> +---- +<1> Writes the value in r1 into the sr0 register from the ss0 subsystem using the command _0x1_ to do so. +<2> Writes the value in pc into the sr32 register from the ss15 subsystem using the command _0x0_ to do so. + +Privileged instruction:: No. (The access control is done at the register/command level). +Updates program state flags:: No. +Exceptions:: PrivFault. + diff --git a/src/execution-engine-spec/instructions/svc.adoc b/src/execution-engine-spec/instructions/svc.adoc new file mode 100644 index 0000000..05c4d64 --- /dev/null +++ b/src/execution-engine-spec/instructions/svc.adoc @@ -0,0 +1,38 @@ +===== SVC: Supervisor Call +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x7f, type: 8, attr: '0x7e'}, + {bits: 25, name: 'svc_num', type: 5} +], config: {label: {right: 'SVC'}}} +.... + +Description:: + Generates an SVC exception to execute a privileged operation. +Encoding:: D2-Type +Assembler syntax:: ++ +[source] +---- +svc +---- ++ +Where: +[horizontal] +svc_num::: + An immediate number identifying the privileged operation to execute. + +Examples:: ++ +[source] +---- +svc 128 <1> +svc 0xff <2> +---- +<1> Calls the privileged operation number 128 that is exposed by the kernel. +<2> Calls the privileged operation number 255 that is exposed by the kernel. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: SVC. + diff --git a/src/execution-engine-spec/subsystems.adoc b/src/execution-engine-spec/subsystems.adoc index 0cc7080..4d09159 100644 --- a/src/execution-engine-spec/subsystems.adoc +++ b/src/execution-engine-spec/subsystems.adoc @@ -30,7 +30,7 @@ The {central-arch-name} allows up to 16 subystem identifiers. Not all of these i |#TODO: Describe it.# |=== - +<<< [id=debugging-subsystem] === Debugging Subsystem ==== Description