Modified A1, B1 and C encodings to remove the condition field
This commit is contained in:
parent
efe9f7da27
commit
90fec87ccb
@ -2,11 +2,11 @@
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 4, name: 'imm[3:0]', type: 5},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 5, name: 'rs2', type: 4},
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{bits: 6, name: 'imm', type: 5}
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{bits: 6, name: 'imm[9:4]', type: 5}
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], config: {label: {right: 'A1-Type'}}}
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....
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@ -26,10 +26,10 @@
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 4, name: 'imm[3:0]', type: 5},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 11, name: 'imm', type: 5}
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{bits: 11, name: 'imm[14:4]', type: 5}
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], config: {label: {right: 'B1-Type'}}}
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....
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@ -48,9 +48,9 @@
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 4, name: 'imm[3:0]', type: 5},
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{bits: 5, name: 'rd', type: 2},
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{bits: 16, name: 'imm', type: 5}
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{bits: 16, name: 'imm[19:4]', type: 5}
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], config: {label: {right: 'C-Type'}}}
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....
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@ -10,97 +10,97 @@
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|0000~2~
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|0000~16~
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|AL
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|al
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|Always
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|_None_
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|0001~2~
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|0001~16~
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|EQ
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|eq
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|Equal
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|Z==1
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|0010~2~
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|0002~16~
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|NEQ
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|ne
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|Not Equal
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|Z==0
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.2+|0011~2~
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.2+|0003~16~
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|UGE
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|ge
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|Unsigned Greater or Equal
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.2+|C==1
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<|CS
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<|cs
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<|Carry Set
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.2+|0100~2~
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.2+|0004~16~
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|ULT
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|lt
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|Unsigned Lower Than
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.2+|C==0
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<|CC
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<|cc
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<|Carry Clear
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|0101~2~
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|0005~16~
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|NEG
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|neg
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|Negative
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|N==1
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|0110~2~
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|0006~16~
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|POS
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|pos
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|Positive
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|N==0
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|0111~2~
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|0007~16~
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|VS
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|vs
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|oVerflow Set
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|V==1
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|1000~2~
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|0008~16~
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|VC
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|vc
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|oVerflow Clear
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|V==0
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|1001~2~
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|0009~16~
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|UGT
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|gt
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|Unsigned Greater Than
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|C==1 && Z==0
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|1010~2~
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|000a~16~
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|ULE
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|le
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|Unsigned Lower or Equal
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|C==0 && Z==1
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|1011~2~
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|000b~16~
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|SGE
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|sge
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|Signed Greater or Equal
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|N==V
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|1100~2~
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|000c~16~
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|SLT
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|slt
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|Signed Lower Than
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|N!=V
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|1101~2~
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|000d~16~
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|SGT
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|sgt
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|Signed Greater Than
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|Z==0 && N==V
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|1110~2~
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|000e~16~
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|SLE
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|sle
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|Signed Lower or Equal
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|Z==1 && N!=V
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@ -33,7 +33,7 @@
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====== BIO: Branch Immediate Offset
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Description::
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Branch to the instruction the address of which is at `pc + off`. +
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The assembler selects this variant over *BAIO* when a condition is given.
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The assembler selects this variant over *BAIO* when a condition other than `al` is given.
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Encoding:: D1-Type
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Assembler syntax::
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+
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@ -53,10 +53,10 @@ Examples::
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+
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[source]
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----
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b.al -20 <1>
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b.ne -20 <1>
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b.eq 8 <2>
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----
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<1> Branches to `pc - 20`.
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<1> If the last comparison resulted in an 'ne' condition status, branches to `pc - 20`. Else, does nothing.
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<2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8`. Else, does nothing.
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Privileged instruction:: No.
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@ -70,17 +70,18 @@ Exceptions::
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Description::
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Branch to the instruction the address of which is at `pc + off`.
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Permits the use of more bits for the offset at the cost of being unconditional. +
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The assembler selects this variant over *BIO* when no condition is given.
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The assembler selects this variant over *BIO* when no condition is given (or when `al` is given).
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Encoding:: D2-Type
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Assembler syntax::
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+
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[source]
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----
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b <off>
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b<cond>? <off>
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition (if specified, can only be `al`).
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off:::
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Signed immediate offset.
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Must be in the range -8388611..8388607.
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@ -90,8 +91,10 @@ Examples::
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[source]
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----
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b -0x3FFFFF <1>
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b.al 0x3FFFFF <2>
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----
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<1> Branches to `pc - 0x3FFFFF`.
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<2> Branches to `pc + 0x3FFFFF`.
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Privileged instruction:: No.
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Updates program state flags:: No.
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@ -3,40 +3,18 @@
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....
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{reg: [
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{bits: 7, name: 0x1, type: 8, attr: '0x01'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 4, name: 'off[3:0]', type: 5},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIR'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x2, type: 8, attr: '0x02'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIRW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x3, type: 8, attr: '0x03'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIOW'}}}
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{bits: 11, name: 'off[14:4]', type: 5}
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], config: {label: {right: 'LDRI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x4, type: 8, attr: '0x04'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 4, name: 'unused'},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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@ -44,56 +22,20 @@
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], config: {label: {right: 'LDRR'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x5, type: 8, attr: '0x05'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDRRW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x6, type: 8, attr: '0x06'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDROW'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|LDRIR
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|<<LDRIR>>
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|LDRIRW
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|<<LDRIRW>>
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|LDRIOW
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|<<LDRIOW>>
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|LDRI
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|<<LDRI>>
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|LDRR
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|<<LDRR>>
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|LDRRW
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|<<LDRRW>>
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|LDROW
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|<<LDROW>>
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|===
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<<<
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[id=LDRIR]
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====== LDRIR: Load Register+Immediate Pre-indexed
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[id=LDRI]
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====== LDRI: Load Register+Immediate
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Description::
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Loads a word from memory into a register.
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The immediate offset `off` is added to the address in the `src` register before reading memory.
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@ -102,112 +44,27 @@ Assembler syntax::
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+
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[source]
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----
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ldr<cond?> <dst>, [<src>, <off?>]
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ldr <dst>, [<src>, <off?>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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dst::: Destination register.
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src::: Source register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range -4096..4092.
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Must be a multiple of 4 and in the range -65536..65532.
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If omitted, then 0 is used.
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Examples::
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+
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[source]
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----
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ldr r1, [r0] <1>
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ldr r3, [r2, 8] <2>
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ldr.eq r5, [r4] <3>
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ldr r1, [r0] <1>
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ldr r3, [r2, 8] <2>
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----
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<1> Reads a word from the memory address in r0 into r1.
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<2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3.
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<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=LDRIRW]
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====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back
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Description::
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Increments the source register then reads a word from memory into the destination register.
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The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register.
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Encoding:: B1-Type
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Assembler syntax::
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+
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[source]
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----
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ldr<cond?> <dst>, ![<src>, <off?>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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dst::: Destination register.
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src::: Source register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range -4096..4092.
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If omitted, then 4 is used.
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Examples::
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+
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[source]
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----
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ldr r1, ![r0] <1>
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ldr r3, ![r2, 8] <2>
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ldr.eq r5, ![r4] <3>
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----
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<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1.
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<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3.
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<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=LDRIOW]
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====== LDRIOW: Load Register+Immediate Post-indexed with Write-back
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Description::
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Reads a word from memory into the destination register then increments the source register.
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The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`.
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Encoding:: B1-Type
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Assembler syntax::
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+
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[source]
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----
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ldr<cond?> <dst>, [<src>, <off?>]!
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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dst::: Destination register.
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src::: Source register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range -4096..4092.
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If omitted, then 4 is used.
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Examples::
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+
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[source]
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----
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ldr r1, [r0]! <1>
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ldr r3, [r2, 8]! <2>
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ldr.eq r5, [r4]! <3>
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----
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<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4.
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<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8.
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<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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@ -216,7 +73,7 @@ Exceptions::
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<<<
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[id=LDRR]
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====== LDRR: Load Register+Register Pre-indexed
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====== LDRR: Load Register+Register
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Description::
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Loads a word from memory into a register.
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The value in the register `off` is added to the address in the `src` register before reading memory.
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@ -225,12 +82,11 @@ Assembler syntax::
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+
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[source]
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----
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ldr<cond?> <dst>, [<src>, <off>]
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ldr <dst>, [<src>, <off>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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dst::: Destination register.
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src::: Source register.
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off::: Offset register.
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@ -239,83 +95,9 @@ Examples::
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+
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[source]
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----
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ldr r1, [sp, r0] <1>
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ldr.eq r0, [r1, r2] <2>
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ldr r1, [sp, r0] <1>
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----
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<1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset.
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<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=LDRRW]
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====== LDRRW: Load Register+Register Pre-indexed with Write-back
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Description::
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Increments the source register then reads a word from memory into the destination register.
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The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register.
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Encoding:: A1-Type
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Assembler syntax::
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+
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[source]
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----
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ldr<cond?> <dst>, ![<src>, <off>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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dst::: Destination register.
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src::: Source register.
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off::: Offset register.
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Examples::
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+
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[source]
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----
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ldr r1, ![sp, r0] <1>
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ldr.eq r0, ![r1, r2] <2>
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----
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<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1.
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<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing.
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|
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Privileged instruction:: No.
|
||||
Updates program state flags:: No.
|
||||
Exceptions::
|
||||
MemFault.
|
||||
|
||||
<<<
|
||||
[id=LDROW]
|
||||
====== LDROW: Load Register+Register Post-indexed with Write-back
|
||||
Description::
|
||||
Reads a word from memory into the destination register then increments the source register.
|
||||
The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`.
|
||||
Encoding:: A1-Type
|
||||
Assembler syntax::
|
||||
+
|
||||
[source]
|
||||
----
|
||||
ldr<cond?> <dst>, [<src>, <off>]!
|
||||
----
|
||||
+
|
||||
Where:
|
||||
[horizontal]
|
||||
cond::: Optional condition.
|
||||
dst::: Destination register.
|
||||
src::: Source register.
|
||||
off::: Offset register.
|
||||
|
||||
Examples::
|
||||
+
|
||||
[source]
|
||||
----
|
||||
ldr r1, [sp, r0]! <1>
|
||||
ldr.eq r0, [r1, r2]! <2>
|
||||
----
|
||||
<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp.
|
||||
<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing.
|
||||
<1> Reads a word from the memory address in sp into r1, using the value of r0 as an offset.
|
||||
|
||||
Privileged instruction:: No.
|
||||
Updates program state flags:: No.
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
....
|
||||
{reg: [
|
||||
{bits: 7, name: 0xd, type: 8, attr: '0x0d'},
|
||||
{bits: 4, name: 'cond', type: 6},
|
||||
{bits: 4, name: 'unused'},
|
||||
{bits: 5, name: 'dst', type: 2},
|
||||
{bits: 5, name: 'src', type: 4},
|
||||
{bits: 11, name: 'unused'}
|
||||
@ -14,9 +14,9 @@
|
||||
....
|
||||
{reg: [
|
||||
{bits: 7, name: 0xe, type: 8, attr: '0x0e'},
|
||||
{bits: 4, name: 'cond', type: 6},
|
||||
{bits: 4, name: 'val[3:0]', type: 5},
|
||||
{bits: 5, name: 'dst', type: 2},
|
||||
{bits: 16, name: 'val', type: 5}
|
||||
{bits: 16, name: 'val[19:4]', type: 5}
|
||||
], config: {label: {right: 'MOVI'}}}
|
||||
....
|
||||
|
||||
@ -41,12 +41,11 @@ Assembler syntax::
|
||||
+
|
||||
[source]
|
||||
----
|
||||
mov<cond?> <dst>, <src>
|
||||
mov <dst>, <src>
|
||||
----
|
||||
+
|
||||
Where:
|
||||
[horizontal]
|
||||
cond::: Optional condition.
|
||||
dst::: Destination register.
|
||||
src::: Source register.
|
||||
|
||||
@ -55,10 +54,8 @@ Examples::
|
||||
[source]
|
||||
----
|
||||
mov r1, r0 <1>
|
||||
mov.lt r3, lr <2>
|
||||
----
|
||||
<1> Copies the value from r0 into r1.
|
||||
<2> If the last comparison resulted in an 'lt' condition status, copies the value from lr into r3. Else, does nothing.
|
||||
|
||||
Privileged instruction:: No.
|
||||
Updates program state flags:: No.
|
||||
@ -76,12 +73,11 @@ Assembler syntax::
|
||||
+
|
||||
[source]
|
||||
----
|
||||
mov<cond?> <dst>, <val>
|
||||
mov <dst>, <val>
|
||||
----
|
||||
+
|
||||
Where:
|
||||
[horizontal]
|
||||
cond::: Optional condition.
|
||||
dst::: Destination register.
|
||||
val::: Immediate value.
|
||||
|
||||
@ -90,10 +86,8 @@ Examples::
|
||||
[source]
|
||||
----
|
||||
mov r0, 42 <1>
|
||||
mov.eq r1, 1337 <2>
|
||||
----
|
||||
<1> Sets r0 to 42.
|
||||
<2> If the last comparison resulted in an 'eq' condition status, sets r1 to 1337. Else, does nothing.
|
||||
|
||||
Privileged instruction:: No.
|
||||
Updates program state flags:: No.
|
||||
|
||||
@ -4,33 +4,32 @@
|
||||
....
|
||||
{reg: [
|
||||
{bits: 7, name: 0x13, type: 8, attr: '0x13'},
|
||||
{bits: 4, name: 'cond', type: 6},
|
||||
{bits: 4, name: 'val[3:0]', type: 5},
|
||||
{bits: 5, name: 'dst', type: 2},
|
||||
{bits: 16, name: 'val', type: 5}
|
||||
{bits: 16, name: 'val[19:4]', type: 5}
|
||||
], config: {label: {right: 'MOVNI'}}}
|
||||
....
|
||||
|
||||
Description::
|
||||
Sets a destination register to the implied negative value given in the immediate field. +
|
||||
The immediate value encoded in the instruction is a 16-bits absolute value.
|
||||
The sign bit is implied to be set, making it a 17-bits signed integer with the last bit always set.
|
||||
The immediate value encoded in the instruction is a 20-bits absolute value.
|
||||
The sign bit is implied to be set, making it a 21-bits signed integer with the last bit always set.
|
||||
The value is sign extended to fit in the 32-bits destination register.
|
||||
Encoding:: C-Type
|
||||
Assembler syntax::
|
||||
+
|
||||
[source]
|
||||
----
|
||||
movn<cond?> <dst>, <val>
|
||||
movn <dst>, <val>
|
||||
----
|
||||
+
|
||||
Where:
|
||||
[horizontal]
|
||||
cond::: Optional condition.
|
||||
dst::: Destination register.
|
||||
val:::
|
||||
Immediate value.
|
||||
The minus sign can be omitted as the value is always negative.
|
||||
The value must be in the range -65636..-1.
|
||||
The value must be in the range -1048576..-1.
|
||||
|
||||
Examples::
|
||||
+
|
||||
@ -38,11 +37,9 @@ Examples::
|
||||
----
|
||||
movn r0, -42 <1>
|
||||
movn r0, 0x10 <2>
|
||||
movn.eq r1, -1337 <3>
|
||||
----
|
||||
<1> Sets r0 to -42.
|
||||
<2> Sets r0 to -0x10. The minus sign is omitted but the immediate value is still treated as being negative.
|
||||
<3> If the last comparison resulted in an 'eq' condition status, sets r1 to -1337. Else, does nothing.
|
||||
|
||||
Privileged instruction:: No.
|
||||
Updates program state flags:: No.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user