diff --git a/src/execution-engine-spec/instruction-formats.adoc b/src/execution-engine-spec/instruction-formats.adoc index e40c417..e004379 100644 --- a/src/execution-engine-spec/instruction-formats.adoc +++ b/src/execution-engine-spec/instruction-formats.adoc @@ -2,11 +2,11 @@ .... {reg: [ {bits: 7, name: 'opcode', type: 8}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'imm[3:0]', type: 5}, {bits: 5, name: 'rd', type: 2}, {bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'rs2', type: 4}, - {bits: 6, name: 'imm', type: 5} + {bits: 6, name: 'imm[9:4]', type: 5} ], config: {label: {right: 'A1-Type'}}} .... @@ -26,10 +26,10 @@ .... {reg: [ {bits: 7, name: 'opcode', type: 8}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'imm[3:0]', type: 5}, {bits: 5, name: 'rd', type: 2}, {bits: 5, name: 'rs1', type: 4}, - {bits: 11, name: 'imm', type: 5} + {bits: 11, name: 'imm[14:4]', type: 5} ], config: {label: {right: 'B1-Type'}}} .... @@ -48,9 +48,9 @@ .... {reg: [ {bits: 7, name: 'opcode', type: 8}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'imm[3:0]', type: 5}, {bits: 5, name: 'rd', type: 2}, - {bits: 16, name: 'imm', type: 5} + {bits: 16, name: 'imm[19:4]', type: 5} ], config: {label: {right: 'C-Type'}}} .... diff --git a/src/execution-engine-spec/instructions-operands-encoding.adoc b/src/execution-engine-spec/instructions-operands-encoding.adoc index bf8c3df..14ff8e6 100644 --- a/src/execution-engine-spec/instructions-operands-encoding.adoc +++ b/src/execution-engine-spec/instructions-operands-encoding.adoc @@ -10,97 +10,97 @@ |0000~2~ |0000~16~ -|AL +|al |Always |_None_ |0001~2~ |0001~16~ -|EQ +|eq |Equal |Z==1 |0010~2~ |0002~16~ -|NEQ +|ne |Not Equal |Z==0 .2+|0011~2~ .2+|0003~16~ -|UGE +|ge |Unsigned Greater or Equal .2+|C==1 -<|CS +<|cs <|Carry Set .2+|0100~2~ .2+|0004~16~ -|ULT +|lt |Unsigned Lower Than .2+|C==0 -<|CC +<|cc <|Carry Clear |0101~2~ |0005~16~ -|NEG +|neg |Negative |N==1 |0110~2~ |0006~16~ -|POS +|pos |Positive |N==0 |0111~2~ |0007~16~ -|VS +|vs |oVerflow Set |V==1 |1000~2~ |0008~16~ -|VC +|vc |oVerflow Clear |V==0 |1001~2~ |0009~16~ -|UGT +|gt |Unsigned Greater Than |C==1 && Z==0 |1010~2~ |000a~16~ -|ULE +|le |Unsigned Lower or Equal |C==0 && Z==1 |1011~2~ |000b~16~ -|SGE +|sge |Signed Greater or Equal |N==V |1100~2~ |000c~16~ -|SLT +|slt |Signed Lower Than |N!=V |1101~2~ |000d~16~ -|SGT +|sgt |Signed Greater Than |Z==0 && N==V |1110~2~ |000e~16~ -|SLE +|sle |Signed Lower or Equal |Z==1 && N!=V diff --git a/src/execution-engine-spec/instructions/b.adoc b/src/execution-engine-spec/instructions/b.adoc index 48b4824..d6c7751 100644 --- a/src/execution-engine-spec/instructions/b.adoc +++ b/src/execution-engine-spec/instructions/b.adoc @@ -33,7 +33,7 @@ ====== BIO: Branch Immediate Offset Description:: Branch to the instruction the address of which is at `pc + off`. + - The assembler selects this variant over *BAIO* when a condition is given. + The assembler selects this variant over *BAIO* when a condition other than `al` is given. Encoding:: D1-Type Assembler syntax:: + @@ -53,10 +53,10 @@ Examples:: + [source] ---- -b.al -20 <1> +b.ne -20 <1> b.eq 8 <2> ---- -<1> Branches to `pc - 20`. +<1> If the last comparison resulted in an 'ne' condition status, branches to `pc - 20`. Else, does nothing. <2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8`. Else, does nothing. Privileged instruction:: No. @@ -70,17 +70,18 @@ Exceptions:: Description:: Branch to the instruction the address of which is at `pc + off`. Permits the use of more bits for the offset at the cost of being unconditional. + - The assembler selects this variant over *BIO* when no condition is given. + The assembler selects this variant over *BIO* when no condition is given (or when `al` is given). Encoding:: D2-Type Assembler syntax:: + [source] ---- -b +b? ---- + Where: [horizontal] +cond::: Optional condition (if specified, can only be `al`). off::: Signed immediate offset. Must be in the range -8388611..8388607. @@ -90,8 +91,10 @@ Examples:: [source] ---- b -0x3FFFFF <1> +b.al 0x3FFFFF <2> ---- <1> Branches to `pc - 0x3FFFFF`. +<2> Branches to `pc + 0x3FFFFF`. Privileged instruction:: No. Updates program state flags:: No. diff --git a/src/execution-engine-spec/instructions/ldr.adoc b/src/execution-engine-spec/instructions/ldr.adoc index 3418905..88b3ae1 100644 --- a/src/execution-engine-spec/instructions/ldr.adoc +++ b/src/execution-engine-spec/instructions/ldr.adoc @@ -3,40 +3,18 @@ .... {reg: [ {bits: 7, name: 0x1, type: 8, attr: '0x01'}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'off[3:0]', type: 5}, {bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'src', type: 4}, - {bits: 11, name: 'off', type: 5} -], config: {label: {right: 'LDRIR'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x2, type: 8, attr: '0x02'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 11, name: 'off', type: 5} -], config: {label: {right: 'LDRIRW'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x3, type: 8, attr: '0x03'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 11, name: 'off', type: 5} -], config: {label: {right: 'LDRIOW'}}} + {bits: 11, name: 'off[14:4]', type: 5} +], config: {label: {right: 'LDRI'}}} .... [wavedrom, ,svg] .... {reg: [ {bits: 7, name: 0x4, type: 8, attr: '0x04'}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'unused'}, {bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'src', type: 4}, {bits: 5, name: 'off', type: 4}, @@ -44,56 +22,20 @@ ], config: {label: {right: 'LDRR'}}} .... -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x5, type: 8, attr: '0x05'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 5, name: 'off', type: 4}, - {bits: 6, name: 'unused'} -], config: {label: {right: 'LDRRW'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x6, type: 8, attr: '0x06'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'dst', type: 2}, - {bits: 5, name: 'src', type: 4}, - {bits: 5, name: 'off', type: 4}, - {bits: 6, name: 'unused'} -], config: {label: {right: 'LDROW'}}} -.... - [frame=ends,grid=rows,cols="1,1"] |=== |Instruction variant | Description -|LDRIR -|<> - -|LDRIRW -|<> - -|LDRIOW -|<> +|LDRI +|<> |LDRR |<> - -|LDRRW -|<> - -|LDROW -|<> |=== <<< -[id=LDRIR] -====== LDRIR: Load Register+Immediate Pre-indexed +[id=LDRI] +====== LDRI: Load Register+Immediate Description:: Loads a word from memory into a register. The immediate offset `off` is added to the address in the `src` register before reading memory. @@ -102,112 +44,27 @@ Assembler syntax:: + [source] ---- -ldr , [, ] +ldr , [, ] ---- + Where: [horizontal] -cond::: Optional condition. dst::: Destination register. src::: Source register. off::: Optional offset immediate. - Must be a multiple of 4 and in the range -4096..4092. + Must be a multiple of 4 and in the range -65536..65532. If omitted, then 0 is used. Examples:: + [source] ---- -ldr r1, [r0] <1> -ldr r3, [r2, 8] <2> -ldr.eq r5, [r4] <3> +ldr r1, [r0] <1> +ldr r3, [r2, 8] <2> ---- <1> Reads a word from the memory address in r0 into r1. <2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3. -<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDRIRW] -====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back -Description:: - Increments the source register then reads a word from memory into the destination register. - The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register. -Encoding:: B1-Type -Assembler syntax:: -+ -[source] ----- -ldr , ![, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: - Optional offset immediate. - Must be a multiple of 4 and in the range -4096..4092. - If omitted, then 4 is used. - -Examples:: -+ -[source] ----- -ldr r1, ![r0] <1> -ldr r3, ![r2, 8] <2> -ldr.eq r5, ![r4] <3> ----- -<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1. -<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3. -<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDRIOW] -====== LDRIOW: Load Register+Immediate Post-indexed with Write-back -Description:: - Reads a word from memory into the destination register then increments the source register. - The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`. -Encoding:: B1-Type -Assembler syntax:: -+ -[source] ----- -ldr , [, ]! ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: - Optional offset immediate. - Must be a multiple of 4 and in the range -4096..4092. - If omitted, then 4 is used. - -Examples:: -+ -[source] ----- -ldr r1, [r0]! <1> -ldr r3, [r2, 8]! <2> -ldr.eq r5, [r4]! <3> ----- -<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4. -<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8. -<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing. Privileged instruction:: No. Updates program state flags:: No. @@ -216,7 +73,7 @@ Exceptions:: <<< [id=LDRR] -====== LDRR: Load Register+Register Pre-indexed +====== LDRR: Load Register+Register Description:: Loads a word from memory into a register. The value in the register `off` is added to the address in the `src` register before reading memory. @@ -225,12 +82,11 @@ Assembler syntax:: + [source] ---- -ldr , [, ] +ldr , [, ] ---- + Where: [horizontal] -cond::: Optional condition. dst::: Destination register. src::: Source register. off::: Offset register. @@ -239,83 +95,9 @@ Examples:: + [source] ---- -ldr r1, [sp, r0] <1> -ldr.eq r0, [r1, r2] <2> +ldr r1, [sp, r0] <1> ---- -<1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset. -<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDRRW] -====== LDRRW: Load Register+Register Pre-indexed with Write-back -Description:: - Increments the source register then reads a word from memory into the destination register. - The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register. -Encoding:: A1-Type -Assembler syntax:: -+ -[source] ----- -ldr , ![, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: Offset register. - -Examples:: -+ -[source] ----- -ldr r1, ![sp, r0] <1> -ldr.eq r0, ![r1, r2] <2> ----- -<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1. -<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=LDROW] -====== LDROW: Load Register+Register Post-indexed with Write-back -Description:: - Reads a word from memory into the destination register then increments the source register. - The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`. -Encoding:: A1-Type -Assembler syntax:: -+ -[source] ----- -ldr , [, ]! ----- -+ -Where: -[horizontal] -cond::: Optional condition. -dst::: Destination register. -src::: Source register. -off::: Offset register. - -Examples:: -+ -[source] ----- -ldr r1, [sp, r0]! <1> -ldr.eq r0, [r1, r2]! <2> ----- -<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp. -<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing. +<1> Reads a word from the memory address in sp into r1, using the value of r0 as an offset. Privileged instruction:: No. Updates program state flags:: No. diff --git a/src/execution-engine-spec/instructions/mov.adoc b/src/execution-engine-spec/instructions/mov.adoc index 7f941c7..5200637 100644 --- a/src/execution-engine-spec/instructions/mov.adoc +++ b/src/execution-engine-spec/instructions/mov.adoc @@ -3,7 +3,7 @@ .... {reg: [ {bits: 7, name: 0xd, type: 8, attr: '0x0d'}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'unused'}, {bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'src', type: 4}, {bits: 11, name: 'unused'} @@ -14,9 +14,9 @@ .... {reg: [ {bits: 7, name: 0xe, type: 8, attr: '0x0e'}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'val[3:0]', type: 5}, {bits: 5, name: 'dst', type: 2}, - {bits: 16, name: 'val', type: 5} + {bits: 16, name: 'val[19:4]', type: 5} ], config: {label: {right: 'MOVI'}}} .... @@ -41,12 +41,11 @@ Assembler syntax:: + [source] ---- -mov , +mov , ---- + Where: [horizontal] -cond::: Optional condition. dst::: Destination register. src::: Source register. @@ -55,10 +54,8 @@ Examples:: [source] ---- mov r1, r0 <1> -mov.lt r3, lr <2> ---- <1> Copies the value from r0 into r1. -<2> If the last comparison resulted in an 'lt' condition status, copies the value from lr into r3. Else, does nothing. Privileged instruction:: No. Updates program state flags:: No. @@ -76,12 +73,11 @@ Assembler syntax:: + [source] ---- -mov , +mov , ---- + Where: [horizontal] -cond::: Optional condition. dst::: Destination register. val::: Immediate value. @@ -90,10 +86,8 @@ Examples:: [source] ---- mov r0, 42 <1> -mov.eq r1, 1337 <2> ---- <1> Sets r0 to 42. -<2> If the last comparison resulted in an 'eq' condition status, sets r1 to 1337. Else, does nothing. Privileged instruction:: No. Updates program state flags:: No. diff --git a/src/execution-engine-spec/instructions/movn.adoc b/src/execution-engine-spec/instructions/movn.adoc index a6e87e7..69654e9 100644 --- a/src/execution-engine-spec/instructions/movn.adoc +++ b/src/execution-engine-spec/instructions/movn.adoc @@ -4,33 +4,32 @@ .... {reg: [ {bits: 7, name: 0x13, type: 8, attr: '0x13'}, - {bits: 4, name: 'cond', type: 6}, + {bits: 4, name: 'val[3:0]', type: 5}, {bits: 5, name: 'dst', type: 2}, - {bits: 16, name: 'val', type: 5} + {bits: 16, name: 'val[19:4]', type: 5} ], config: {label: {right: 'MOVNI'}}} .... Description:: Sets a destination register to the implied negative value given in the immediate field. + - The immediate value encoded in the instruction is a 16-bits absolute value. - The sign bit is implied to be set, making it a 17-bits signed integer with the last bit always set. + The immediate value encoded in the instruction is a 20-bits absolute value. + The sign bit is implied to be set, making it a 21-bits signed integer with the last bit always set. The value is sign extended to fit in the 32-bits destination register. Encoding:: C-Type Assembler syntax:: + [source] ---- -movn , +movn , ---- + Where: [horizontal] -cond::: Optional condition. dst::: Destination register. val::: Immediate value. The minus sign can be omitted as the value is always negative. - The value must be in the range -65636..-1. + The value must be in the range -1048576..-1. Examples:: + @@ -38,11 +37,9 @@ Examples:: ---- movn r0, -42 <1> movn r0, 0x10 <2> -movn.eq r1, -1337 <3> ---- <1> Sets r0 to -42. <2> Sets r0 to -0x10. The minus sign is omitted but the immediate value is still treated as being negative. -<3> If the last comparison resulted in an 'eq' condition status, sets r1 to -1337. Else, does nothing. Privileged instruction:: No. Updates program state flags:: No.