Moved some "b" instruction variants under the "bx" instruction
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@ -37,6 +37,8 @@ include::instructions/mov.adoc[]
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<<<
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==== Branching Instructions
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include::instructions/b.adoc[]
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<<<
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include::instructions/bx.adoc[]
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<<<
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==== Subsystems Instructions
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@ -17,38 +17,6 @@
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], config: {label: {right: 'BAIO'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x11, type: 8, attr: '0x11'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'off[4:0]', type: 5},
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{bits: 5, name: 'base', type: 4},
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{bits: 11, name: 'off[15:5]', type: 5}
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], config: {label: {right: 'BRIA'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x12, type: 8, attr: '0x12'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'unused'},
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{bits: 5, name: 'base', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'BRRA'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x13, type: 8, attr: '0x13'},
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{bits: 1, name: 0},
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{bits: 24, name: 'addr', type: 5}
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], config: {label: {right: 'BAIA'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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@ -58,18 +26,8 @@
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|BAIO
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|<<BAIO>>
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|BRIA
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|<<BRIA>>
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|BRRA
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|<<BRRA>>
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|BAIA
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|<<BAIA>>
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|===
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<<<
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[id=BIO]
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====== BIO: Branch Immediate Offset
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@ -136,106 +94,3 @@ Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=BRIA]
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====== BRIA: Branch Register+Immediate Absolute
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Description::
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Branch to the instruction the address of which is at `base + off`.
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Permits to use a varying base address with a fixed offset.
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Encoding:: B2-Type
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Assembler syntax::
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+
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[source]
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----
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b<cond?> [<base>, <off?>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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base::: Base register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range 0-262140.
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If omitted, then 0 is used.
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Examples::
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+
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[source]
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----
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b [r0, 12] <1>
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b.eq [r3] <2>
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----
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<1> Branches to the instruction at address `r0 + 12`.
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<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=BRRA]
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====== BRRA: Branch Register+Register Absolute
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Description::
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Branch to the instruction the address of which is at `base + off`.
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Permits to use a varying base address with a varying offset.
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Encoding:: A2-Type
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Assembler syntax::
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+
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[source]
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----
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b<cond?> [<base>, <off>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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base::: Base register.
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off::: Offset register.
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Examples::
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+
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[source]
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----
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b [r0, r1] <1>
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b.eq [r2, r3] <2>
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----
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<1> Branches to the instruction at address `r0 + r1`.
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<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3`. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=BAIA]
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====== BAIA: Branch Always Immediate Address
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Description::
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Branch to the instruction at the address `addr`.
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Encoding:: D2-Type
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Assembler syntax::
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+
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[source]
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----
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b <addr>
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----
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+
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Where:
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[horizontal]
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addr::: Immediate address.
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Examples::
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+
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[source]
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----
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b 0x100000 <1>
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----
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<1> Branches to the address 0x100000.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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108
src/execution-engine-spec/instructions/bx.adoc
Normal file
108
src/execution-engine-spec/instructions/bx.adoc
Normal file
@ -0,0 +1,108 @@
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===== BX: Branch Extended
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x11, type: 8, attr: '0x11'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'off[4:0]', type: 5},
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{bits: 5, name: 'base', type: 4},
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{bits: 11, name: 'off[15:5]', type: 5}
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], config: {label: {right: 'BXI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x12, type: 8, attr: '0x12'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'unused'},
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{bits: 5, name: 'base', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'BXR'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|BXI
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|<<BXI>>
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|BXR
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|<<BXR>>
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|===
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<<<
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[id=BXI]
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====== BXI: Branch Extended Immediate
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Description::
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Branch to the instruction the address of which is at `base + off`.
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Permits to use a varying base address with a fixed offset.
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Encoding:: B2-Type
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Assembler syntax::
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+
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[source]
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----
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bx<cond?> [<base>, <off?>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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base::: Base register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range 0-262140.
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If omitted, then 0 is used.
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Examples::
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+
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[source]
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----
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bx [r0, 12] <1>
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bx.eq [r3] <2>
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----
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<1> Branches to the instruction at address `r0 + 12`.
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<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=BXR]
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====== BXR: Branch Extended Register
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Description::
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Branch to the instruction the address of which is at `base + off`.
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Permits to use a varying base address with a varying offset.
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Encoding:: A2-Type
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Assembler syntax::
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+
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[source]
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----
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bx<cond?> [<base>, <off>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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base::: Base register.
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off::: Offset register.
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Examples::
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+
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[source]
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----
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bx [r0, r1] <1>
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bx.eq [r2, r3] <2>
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----
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<1> Branches to the instruction at address `r0 + r1`.
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<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3`. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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