diff --git a/src/execution-engine-spec/instructions.adoc b/src/execution-engine-spec/instructions.adoc index b65f844..bbaee78 100644 --- a/src/execution-engine-spec/instructions.adoc +++ b/src/execution-engine-spec/instructions.adoc @@ -37,6 +37,8 @@ include::instructions/mov.adoc[] <<< ==== Branching Instructions include::instructions/b.adoc[] +<<< +include::instructions/bx.adoc[] <<< ==== Subsystems Instructions diff --git a/src/execution-engine-spec/instructions/b.adoc b/src/execution-engine-spec/instructions/b.adoc index 6f4b169..6c4cfe6 100644 --- a/src/execution-engine-spec/instructions/b.adoc +++ b/src/execution-engine-spec/instructions/b.adoc @@ -17,38 +17,6 @@ ], config: {label: {right: 'BAIO'}}} .... -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x11, type: 8, attr: '0x11'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'off[4:0]', type: 5}, - {bits: 5, name: 'base', type: 4}, - {bits: 11, name: 'off[15:5]', type: 5} -], config: {label: {right: 'BRIA'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x12, type: 8, attr: '0x12'}, - {bits: 4, name: 'cond', type: 6}, - {bits: 5, name: 'unused'}, - {bits: 5, name: 'base', type: 4}, - {bits: 5, name: 'off', type: 4}, - {bits: 6, name: 'unused'} -], config: {label: {right: 'BRRA'}}} -.... - -[wavedrom, ,svg] -.... -{reg: [ - {bits: 7, name: 0x13, type: 8, attr: '0x13'}, - {bits: 1, name: 0}, - {bits: 24, name: 'addr', type: 5} -], config: {label: {right: 'BAIA'}}} -.... - [frame=ends,grid=rows,cols="1,1"] |=== |Instruction variant | Description @@ -58,18 +26,8 @@ |BAIO |<> - -|BRIA -|<> - -|BRRA -|<> - -|BAIA -|<> |=== - <<< [id=BIO] ====== BIO: Branch Immediate Offset @@ -136,106 +94,3 @@ Updates program state flags:: No. Exceptions:: MemFault. -<<< -[id=BRIA] -====== BRIA: Branch Register+Immediate Absolute -Description:: - Branch to the instruction the address of which is at `base + off`. - Permits to use a varying base address with a fixed offset. -Encoding:: B2-Type -Assembler syntax:: -+ -[source] ----- -b [, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -base::: Base register. -off::: - Optional offset immediate. - Must be a multiple of 4 and in the range 0-262140. - If omitted, then 0 is used. - -Examples:: -+ -[source] ----- -b [r0, 12] <1> -b.eq [r3] <2> ----- -<1> Branches to the instruction at address `r0 + 12`. -<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=BRRA] -====== BRRA: Branch Register+Register Absolute -Description:: - Branch to the instruction the address of which is at `base + off`. - Permits to use a varying base address with a varying offset. -Encoding:: A2-Type -Assembler syntax:: -+ -[source] ----- -b [, ] ----- -+ -Where: -[horizontal] -cond::: Optional condition. -base::: Base register. -off::: Offset register. - -Examples:: -+ -[source] ----- -b [r0, r1] <1> -b.eq [r2, r3] <2> ----- -<1> Branches to the instruction at address `r0 + r1`. -<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3`. Else, does nothing. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - -<<< -[id=BAIA] -====== BAIA: Branch Always Immediate Address -Description:: - Branch to the instruction at the address `addr`. -Encoding:: D2-Type -Assembler syntax:: -+ -[source] ----- -b ----- -+ -Where: -[horizontal] -addr::: Immediate address. - -Examples:: -+ -[source] ----- -b 0x100000 <1> ----- -<1> Branches to the address 0x100000. - -Privileged instruction:: No. -Updates program state flags:: No. -Exceptions:: - MemFault. - diff --git a/src/execution-engine-spec/instructions/bx.adoc b/src/execution-engine-spec/instructions/bx.adoc new file mode 100644 index 0000000..55c69ad --- /dev/null +++ b/src/execution-engine-spec/instructions/bx.adoc @@ -0,0 +1,108 @@ +===== BX: Branch Extended +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x11, type: 8, attr: '0x11'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'off[4:0]', type: 5}, + {bits: 5, name: 'base', type: 4}, + {bits: 11, name: 'off[15:5]', type: 5} +], config: {label: {right: 'BXI'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x12, type: 8, attr: '0x12'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'unused'}, + {bits: 5, name: 'base', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'BXR'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|BXI +|<> + +|BXR +|<> +|=== + +<<< +[id=BXI] +====== BXI: Branch Extended Immediate +Description:: + Branch to the instruction the address of which is at `base + off`. + Permits to use a varying base address with a fixed offset. +Encoding:: B2-Type +Assembler syntax:: ++ +[source] +---- +bx [, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +base::: Base register. +off::: + Optional offset immediate. + Must be a multiple of 4 and in the range 0-262140. + If omitted, then 0 is used. + +Examples:: ++ +[source] +---- +bx [r0, 12] <1> +bx.eq [r3] <2> +---- +<1> Branches to the instruction at address `r0 + 12`. +<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=BXR] +====== BXR: Branch Extended Register +Description:: + Branch to the instruction the address of which is at `base + off`. + Permits to use a varying base address with a varying offset. +Encoding:: A2-Type +Assembler syntax:: ++ +[source] +---- +bx [, ] +---- ++ +Where: +[horizontal] +cond::: Optional condition. +base::: Base register. +off::: Offset register. + +Examples:: ++ +[source] +---- +bx [r0, r1] <1> +bx.eq [r2, r3] <2> +---- +<1> Branches to the instruction at address `r0 + r1`. +<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3`. Else, does nothing. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. +