Added str, strh and strc instructions
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@ -40,6 +40,7 @@ include::instructions/svc.adoc[]
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<<<
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<<<
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==== Memory-Related Instructions
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==== Memory-Related Instructions
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.Memory read instructions
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[frame=ends,grid=rows,cols="1,1"]
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|===
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|Instruction | Description
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|Instruction | Description
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@ -53,12 +54,32 @@ include::instructions/svc.adoc[]
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|LDRC
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|LDRC
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|<<LDRCINSTR>>
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|<<LDRCINSTR>>
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|===
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|===
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.Memory write instructions
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction | Description
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|STR
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|<<STRINSTR>>
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|STRH
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|<<STRHINSTR>>
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|STRC
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|<<STRCINSTR>>
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|===
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<<<
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<<<
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include::instructions/ldr.adoc[]
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include::instructions/ldr.adoc[]
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<<<
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<<<
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include::instructions/ldrh.adoc[]
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include::instructions/ldrh.adoc[]
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<<<
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<<<
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include::instructions/ldrc.adoc[]
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include::instructions/ldrc.adoc[]
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<<<
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include::instructions/str.adoc[]
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<<<
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include::instructions/strh.adoc[]
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<<<
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include::instructions/strc.adoc[]
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<<<
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<<<
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==== Register Manipulation Instructions
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==== Register Manipulation Instructions
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@ -38,7 +38,7 @@
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[id=LDRHI]
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[id=LDRHI]
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====== LDRHI: Load Halfword Register+Immediate
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====== LDRHI: Load Halfword Register+Immediate
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Description::
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Description::
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Loads a halfword from memory into a register.
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Loads an halfword from memory into a register.
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The immediate offset `off` is added to the address in the `src` register before reading memory.
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The immediate offset `off` is added to the address in the `src` register before reading memory.
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Encoding:: B1-Type
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Encoding:: B1-Type
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Assembler syntax::
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Assembler syntax::
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@ -64,8 +64,8 @@ Examples::
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ldrh r1, [r0] <1>
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ldrh r1, [r0] <1>
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ldrh r3, [r2, 8] <2>
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ldrh r3, [r2, 8] <2>
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----
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----
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<1> Reads a halfword from the memory address in r0 into r1.
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<1> Reads an halfword from the memory address in r0 into r1.
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<2> Reads a halfword from the memory address in r2, with an 8 bytes offset, into r3.
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<2> Reads an halfword from the memory address in r2, with an 8 bytes offset, into r3.
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Privileged instruction:: No.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Updates program state flags:: No.
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@ -76,7 +76,7 @@ Exceptions::
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[id=LDRHR]
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[id=LDRHR]
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====== LDRHR: Load Halfword Register+Register
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====== LDRHR: Load Halfword Register+Register
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Description::
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Description::
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Loads a halfword from memory into a register.
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Loads an halfword from memory into a register.
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The value in the register `off` is added to the address in the `src` register before reading memory.
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The value in the register `off` is added to the address in the `src` register before reading memory.
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Encoding:: A1-Type
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Encoding:: A1-Type
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Assembler syntax::
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Assembler syntax::
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@ -98,7 +98,7 @@ Examples::
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----
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----
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ldrh r1, [sp, r0] <1>
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ldrh r1, [sp, r0] <1>
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----
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----
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<1> Reads a halfword from the memory address in sp into r1, using the value of r0 as an offset.
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<1> Reads an halfword from the memory address in sp into r1, using the value of r0 as an offset.
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Privileged instruction:: No.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Updates program state flags:: No.
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107
src/execution-engine-spec/instructions/str.adoc
Normal file
107
src/execution-engine-spec/instructions/str.adoc
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@ -0,0 +1,107 @@
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[id=STRINSTR]
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===== STR: Store Register
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x18, type: 8, attr: '0x18'},
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{bits: 4, name: 'off[3:0]', type: 5},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off[14:4]', type: 5}
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], config: {label: {right: 'STRI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x19, type: 8, attr: '0x19'},
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{bits: 4, name: 'unused'},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'STRR'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|STRI
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|<<STRI>>
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|STRR
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|<<STRR>>
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|===
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<<<
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[id=STRI]
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====== STRI: Store Register+Immediate
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Description::
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Stores a word in a register into memory.
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The immediate offset `off` is added to the address in the `dst` register before writing memory.
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Encoding:: B1-Type
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Assembler syntax::
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+
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[source]
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----
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str [<dst>, <off?>], <src>
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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off:::
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Optional offset immediate.
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Must be a multiple of 4 and in the range -65536..65532.
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If omitted, then 0 is used.
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src::: Source register.
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Examples::
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+
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[source]
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----
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str [r0], r1 <1>
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str [r2, 8], r3 <2>
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----
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<1> Stores a word from r1 at the memory address in r0.
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<2> Stores a word from r3 at the memory address in r2, with an 8 bytes offset.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=STRR]
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====== STRR: Store Register+Register
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Description::
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Stores a word in a register into memory.
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The value in the register `off` is added to the address in the `dst` register before writing memory.
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Encoding:: A1-Type
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Assembler syntax::
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+
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[source]
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----
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str [<dst>, <off>], <src>
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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off::: Offset register.
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src::: Source register.
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Examples::
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+
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[source]
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----
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str [sp, r0], r1 <1>
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----
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<1> Stores a word from r1 at the memory address in sp, using the value of r0 as an offset.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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107
src/execution-engine-spec/instructions/strc.adoc
Normal file
107
src/execution-engine-spec/instructions/strc.adoc
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@ -0,0 +1,107 @@
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[id=STRCINSTR]
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===== STRC: Store Register Character
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x1b, type: 8, attr: '0x1b'},
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{bits: 4, name: 'off[3:0]', type: 5},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off[14:4]', type: 5}
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], config: {label: {right: 'STRCI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x1c, type: 8, attr: '0x1c'},
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{bits: 4, name: 'unused'},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'STRCR'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|STRCI
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|<<STRCI>>
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|STRCR
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|<<STRCR>>
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|===
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<<<
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[id=STRCI]
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====== STRCI: Store Character Register+Immediate
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Description::
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Stores a character (or byte) in a register into memory.
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The immediate offset `off` is added to the address in the `dst` register before writing memory.
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Encoding:: B1-Type
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Assembler syntax::
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+
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[source]
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----
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strc [<dst>, <off?>], <src>
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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off:::
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Optional offset immediate.
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Must be in the range -16384..16383.
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If omitted, then 0 is used.
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src::: Source register.
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Examples::
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+
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[source]
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----
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strc [r0], r1 <1>
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strc [r2, 8], r3 <2>
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----
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<1> Stores a character from r1 at the memory address in r0.
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<2> Stores a character from r3 at the memory address in r2, with an 8 bytes offset.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=STRCR]
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====== STRCR: Store Character Register+Register
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Description::
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Stores a character (or byte) in a register into memory.
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The value in the register `off` is added to the address in the `dst` register before writing memory.
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Encoding:: A1-Type
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Assembler syntax::
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+
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[source]
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----
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strc [<dst>, <off>], <src>
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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off::: Offset register.
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src::: Source register.
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Examples::
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+
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[source]
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----
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strc [sp, r0], r1 <1>
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----
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<1> Stores a character from r1 at the memory address in sp, using the value of r0 as an offset.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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107
src/execution-engine-spec/instructions/strh.adoc
Normal file
107
src/execution-engine-spec/instructions/strh.adoc
Normal file
@ -0,0 +1,107 @@
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[id=STRHINSTR]
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===== STRH: Store Register Halfword
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x19, type: 8, attr: '0x19'},
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{bits: 4, name: 'off[3:0]', type: 5},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off[14:4]', type: 5}
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], config: {label: {right: 'STRHI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x1a, type: 8, attr: '0x1a'},
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{bits: 4, name: 'unused'},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'STRHR'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|STRHI
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|<<STRHI>>
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|STRHR
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|<<STRHR>>
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|===
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<<<
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[id=STRHI]
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====== STRHI: Store Halfword Register+Immediate
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Description::
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Stores an halfword in a register into memory.
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The immediate offset `off` is added to the address in the `dst` register before writing memory.
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Encoding:: B1-Type
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Assembler syntax::
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+
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[source]
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----
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strh [<dst>, <off?>], <src>
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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off:::
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Optional offset immediate.
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Must be a multiple of 2 and in the range -32768..32766.
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If omitted, then 0 is used.
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src::: Source register.
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Examples::
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+
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[source]
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----
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strh [r0], r1 <1>
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strh [r2, 8], r3 <2>
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----
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<1> Stores an halfword from r1 at the memory address in r0.
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<2> Stores an halfword from r3 at the memory address in r2, with an 8 bytes offset.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=STRHR]
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====== STRHR: Store Halfword Register+Register
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Description::
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Stores an halfword in a register into memory.
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The value in the register `off` is added to the address in the `dst` register before writing memory.
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Encoding:: A1-Type
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Assembler syntax::
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+
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[source]
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----
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strh [<dst>, <off>], <src>
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----
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+
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Where:
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[horizontal]
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dst::: Destination register.
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off::: Offset register.
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src::: Source register.
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|
||||||
|
Examples::
|
||||||
|
+
|
||||||
|
[source]
|
||||||
|
----
|
||||||
|
strh [sp, r0], r1 <1>
|
||||||
|
----
|
||||||
|
<1> Stores an halfword from r1 at the memory address in sp, using the value of r0 as an offset.
|
||||||
|
|
||||||
|
Privileged instruction:: No.
|
||||||
|
Updates program state flags:: No.
|
||||||
|
Exceptions::
|
||||||
|
MemFault.
|
||||||
|
|
||||||
Loading…
Reference in New Issue
Block a user