diff --git a/src/execution-engine-spec/instructions.adoc b/src/execution-engine-spec/instructions.adoc index 06827c1..12d4983 100644 --- a/src/execution-engine-spec/instructions.adoc +++ b/src/execution-engine-spec/instructions.adoc @@ -40,6 +40,7 @@ include::instructions/svc.adoc[] <<< ==== Memory-Related Instructions +.Memory read instructions [frame=ends,grid=rows,cols="1,1"] |=== |Instruction | Description @@ -53,12 +54,32 @@ include::instructions/svc.adoc[] |LDRC |<> |=== +.Memory write instructions +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction | Description + +|STR +|<> + +|STRH +|<> + +|STRC +|<> +|=== <<< include::instructions/ldr.adoc[] <<< include::instructions/ldrh.adoc[] <<< include::instructions/ldrc.adoc[] +<<< +include::instructions/str.adoc[] +<<< +include::instructions/strh.adoc[] +<<< +include::instructions/strc.adoc[] <<< ==== Register Manipulation Instructions diff --git a/src/execution-engine-spec/instructions/ldrh.adoc b/src/execution-engine-spec/instructions/ldrh.adoc index 2ce1cd5..366d5bd 100644 --- a/src/execution-engine-spec/instructions/ldrh.adoc +++ b/src/execution-engine-spec/instructions/ldrh.adoc @@ -38,7 +38,7 @@ [id=LDRHI] ====== LDRHI: Load Halfword Register+Immediate Description:: - Loads a halfword from memory into a register. + Loads an halfword from memory into a register. The immediate offset `off` is added to the address in the `src` register before reading memory. Encoding:: B1-Type Assembler syntax:: @@ -64,8 +64,8 @@ Examples:: ldrh r1, [r0] <1> ldrh r3, [r2, 8] <2> ---- -<1> Reads a halfword from the memory address in r0 into r1. -<2> Reads a halfword from the memory address in r2, with an 8 bytes offset, into r3. +<1> Reads an halfword from the memory address in r0 into r1. +<2> Reads an halfword from the memory address in r2, with an 8 bytes offset, into r3. Privileged instruction:: No. Updates program state flags:: No. @@ -76,7 +76,7 @@ Exceptions:: [id=LDRHR] ====== LDRHR: Load Halfword Register+Register Description:: - Loads a halfword from memory into a register. + Loads an halfword from memory into a register. The value in the register `off` is added to the address in the `src` register before reading memory. Encoding:: A1-Type Assembler syntax:: @@ -98,7 +98,7 @@ Examples:: ---- ldrh r1, [sp, r0] <1> ---- -<1> Reads a halfword from the memory address in sp into r1, using the value of r0 as an offset. +<1> Reads an halfword from the memory address in sp into r1, using the value of r0 as an offset. Privileged instruction:: No. Updates program state flags:: No. diff --git a/src/execution-engine-spec/instructions/str.adoc b/src/execution-engine-spec/instructions/str.adoc new file mode 100644 index 0000000..27c7571 --- /dev/null +++ b/src/execution-engine-spec/instructions/str.adoc @@ -0,0 +1,107 @@ +[id=STRINSTR] +===== STR: Store Register +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x18, type: 8, attr: '0x18'}, + {bits: 4, name: 'off[3:0]', type: 5}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off[14:4]', type: 5} +], config: {label: {right: 'STRI'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x19, type: 8, attr: '0x19'}, + {bits: 4, name: 'unused'}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'STRR'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|STRI +|<> + +|STRR +|<> +|=== + +<<< +[id=STRI] +====== STRI: Store Register+Immediate +Description:: + Stores a word in a register into memory. + The immediate offset `off` is added to the address in the `dst` register before writing memory. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +str [, ], +---- ++ +Where: +[horizontal] +dst::: Destination register. +off::: + Optional offset immediate. + Must be a multiple of 4 and in the range -65536..65532. + If omitted, then 0 is used. +src::: Source register. + +Examples:: ++ +[source] +---- +str [r0], r1 <1> +str [r2, 8], r3 <2> +---- +<1> Stores a word from r1 at the memory address in r0. +<2> Stores a word from r3 at the memory address in r2, with an 8 bytes offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=STRR] +====== STRR: Store Register+Register +Description:: + Stores a word in a register into memory. + The value in the register `off` is added to the address in the `dst` register before writing memory. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +str [, ], +---- ++ +Where: +[horizontal] +dst::: Destination register. +off::: Offset register. +src::: Source register. + +Examples:: ++ +[source] +---- +str [sp, r0], r1 <1> +---- +<1> Stores a word from r1 at the memory address in sp, using the value of r0 as an offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + diff --git a/src/execution-engine-spec/instructions/strc.adoc b/src/execution-engine-spec/instructions/strc.adoc new file mode 100644 index 0000000..f719421 --- /dev/null +++ b/src/execution-engine-spec/instructions/strc.adoc @@ -0,0 +1,107 @@ +[id=STRCINSTR] +===== STRC: Store Register Character +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x1b, type: 8, attr: '0x1b'}, + {bits: 4, name: 'off[3:0]', type: 5}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off[14:4]', type: 5} +], config: {label: {right: 'STRCI'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x1c, type: 8, attr: '0x1c'}, + {bits: 4, name: 'unused'}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'STRCR'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|STRCI +|<> + +|STRCR +|<> +|=== + +<<< +[id=STRCI] +====== STRCI: Store Character Register+Immediate +Description:: + Stores a character (or byte) in a register into memory. + The immediate offset `off` is added to the address in the `dst` register before writing memory. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +strc [, ], +---- ++ +Where: +[horizontal] +dst::: Destination register. +off::: + Optional offset immediate. + Must be in the range -16384..16383. + If omitted, then 0 is used. +src::: Source register. + +Examples:: ++ +[source] +---- +strc [r0], r1 <1> +strc [r2, 8], r3 <2> +---- +<1> Stores a character from r1 at the memory address in r0. +<2> Stores a character from r3 at the memory address in r2, with an 8 bytes offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=STRCR] +====== STRCR: Store Character Register+Register +Description:: + Stores a character (or byte) in a register into memory. + The value in the register `off` is added to the address in the `dst` register before writing memory. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +strc [, ], +---- ++ +Where: +[horizontal] +dst::: Destination register. +off::: Offset register. +src::: Source register. + +Examples:: ++ +[source] +---- +strc [sp, r0], r1 <1> +---- +<1> Stores a character from r1 at the memory address in sp, using the value of r0 as an offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + diff --git a/src/execution-engine-spec/instructions/strh.adoc b/src/execution-engine-spec/instructions/strh.adoc new file mode 100644 index 0000000..3dc6cd7 --- /dev/null +++ b/src/execution-engine-spec/instructions/strh.adoc @@ -0,0 +1,107 @@ +[id=STRHINSTR] +===== STRH: Store Register Halfword +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x19, type: 8, attr: '0x19'}, + {bits: 4, name: 'off[3:0]', type: 5}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off[14:4]', type: 5} +], config: {label: {right: 'STRHI'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x1a, type: 8, attr: '0x1a'}, + {bits: 4, name: 'unused'}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'STRHR'}}} +.... + +[frame=ends,grid=rows,cols="1,1"] +|=== +|Instruction variant | Description + +|STRHI +|<> + +|STRHR +|<> +|=== + +<<< +[id=STRHI] +====== STRHI: Store Halfword Register+Immediate +Description:: + Stores an halfword in a register into memory. + The immediate offset `off` is added to the address in the `dst` register before writing memory. +Encoding:: B1-Type +Assembler syntax:: ++ +[source] +---- +strh [, ], +---- ++ +Where: +[horizontal] +dst::: Destination register. +off::: + Optional offset immediate. + Must be a multiple of 2 and in the range -32768..32766. + If omitted, then 0 is used. +src::: Source register. + +Examples:: ++ +[source] +---- +strh [r0], r1 <1> +strh [r2, 8], r3 <2> +---- +<1> Stores an halfword from r1 at the memory address in r0. +<2> Stores an halfword from r3 at the memory address in r2, with an 8 bytes offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. + +<<< +[id=STRHR] +====== STRHR: Store Halfword Register+Register +Description:: + Stores an halfword in a register into memory. + The value in the register `off` is added to the address in the `dst` register before writing memory. +Encoding:: A1-Type +Assembler syntax:: ++ +[source] +---- +strh [, ], +---- ++ +Where: +[horizontal] +dst::: Destination register. +off::: Offset register. +src::: Source register. + +Examples:: ++ +[source] +---- +strh [sp, r0], r1 <1> +---- +<1> Stores an halfword from r1 at the memory address in sp, using the value of r0 as an offset. + +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: + MemFault. +