Added the adr instruction
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Elyan 2024-11-11 16:57:14 +01:00
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commit 48bdcb9f66
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@ -32,11 +32,16 @@ include::instructions-operands-encoding.adoc[]
|SVC |SVC
|<<SVCINSTR>> |<<SVCINSTR>>
|ADR
|<<ADRINSTR>>
|=== |===
<<< <<<
include::instructions/nop.adoc[] include::instructions/nop.adoc[]
<<< <<<
include::instructions/svc.adoc[] include::instructions/svc.adoc[]
<<<
include::instructions/adr.adoc[]
<<< <<<
==== Memory-Related Instructions ==== Memory-Related Instructions

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@ -0,0 +1,45 @@
[id=ADRINSTR]
===== ADR : Address from PC-relative offset
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x1d, type: 8, attr: '0x1d'},
{bits: 4, name: 'off[3:0]', type: 5},
{bits: 5, name: 'dst', type: 2},
{bits: 16, name: 'off[19:4]', type: 5}
], config: {label: {right: 'ADRI'}}}
....
Description::
Constructs an absolute address from a given *pc*-relative offset and stores it in a given register.
Sets the `dst` register to the value of `pc + off`.
Encoding:: C-Type
Assembler syntax::
+
[source]
----
adr <dst>, <off>
----
+
Where:
[horizontal]
dst::: Destination register.
off:::
Immediate offset.
Must be in the range -524288..524287.
Examples::
+
[source]
----
adr r0, -48 <1>
adr r1, 0x1234 <2>
----
<1> Sets r0 to `pc - 48`.
<2> Sets r1 to `pc + 0x1234`.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
None.