Added an index to the instruction variants for each instruction

src/execution-engine-spec/instructions.adoc

@@ -23,12 +23,37 @@ include::instructions-operands-encoding.adoc[]
 * system mode instructions (svc, uret, sret, ...)
 
 ==== Miscellaneous Instructions
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction | Description
+
+|NOP
+|<<NOPINSTR>>
+
+|SVC
+|<<SVCINSTR>>
+|===
+<<<
 include::instructions/nop.adoc[]
 <<<
 include::instructions/svc.adoc[]
 
 <<<
 ==== Memory-Related Instructions
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction | Description
+
+|LDR
+|<<LDRINSTR>>
+
+|LDRH
+|<<LDRHINSTR>>
+
+|LDRC
+|<<LDRCINSTR>>
+|===
+<<<
 include::instructions/ldr.adoc[]
 <<<
 include::instructions/ldrh.adoc[]
@@ -37,12 +62,40 @@ include::instructions/ldrc.adoc[]
 
 <<<
 ==== Register Manipulation Instructions
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction | Description
+
+|MOV
+|<<MOVINSTR>>
+
+|MOVN
+|<<MOVNINSTR>>
+|===
+<<<
 include::instructions/mov.adoc[]
 <<<
 include::instructions/movn.adoc[]
 
 <<<
 ==== Branching Instructions
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction | Description
+
+|B
+|<<BINSTR>>
+
+|BX
+|<<BXINSTR>>
+
+|BL
+|<<BLINSTR>>
+
+|BLX
+|<<BLXINSTR>>
+|===
+<<<
 include::instructions/b.adoc[]
 <<<
 include::instructions/bx.adoc[]
@@ -53,6 +106,17 @@ include::instructions/blx.adoc[]
 
 <<<
 ==== Subsystems Instructions
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction | Description
+
+|SSR
+|<<SSRINSTR>>
+
+|SSW
+|<<SSWINSTR>>
+|===
+<<<
 include::instructions/ssr.adoc[]
 <<<
 include::instructions/ssw.adoc[]

src/execution-engine-spec/instructions/b.adoc

@@ -1,3 +1,4 @@
+[id=BINSTR]
 ===== B: Branch
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/bl.adoc

@@ -1,3 +1,4 @@
+[id=BLINSTR]
 ===== BL: Branch with Link
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/blx.adoc

@@ -1,3 +1,4 @@
+[id=BLXINSTR]
 ===== BLX: Branch with Link Extended
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/bx.adoc

@@ -1,3 +1,4 @@
+[id=BXINSTR]
 ===== BX: Branch Extended
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/ldr.adoc

@@ -1,3 +1,4 @@
+[id=LDRINSTR]
 ===== LDR: Load Register
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/ldrc.adoc

@@ -1,3 +1,4 @@
+[id=LDRCINSTR]
 ===== LDRC: Load Register Character
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/ldrh.adoc

@@ -1,3 +1,4 @@
+[id=LDRHINSTR]
 ===== LDRH: Load Register Halfword
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/mov.adoc

@@ -1,3 +1,4 @@
+[id=MOVINSTR]
 ===== MOV: Move to Register
 [wavedrom, ,svg]
 ....
@@ -67,7 +68,7 @@ Exceptions::
 ====== MOVI: Move Immediate to Register
 Description::
     Sets a destination register to the value given in the immediate field. +
-    To set a negative value, use <<MOVNI>>.
+    To set a negative value, use <<MOVNINSTR>>.
 Encoding:: C-Type
 Assembler syntax::
 +

src/execution-engine-spec/instructions/movn.adoc

@@ -1,4 +1,4 @@
-[id=MOVNI]
+[id=MOVNINSTR]
 ===== MOVN: Move Negative Immediate to Register
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/nop.adoc

@@ -1,4 +1,4 @@
-[id=NOP]
+[id=NOPINSTR]
 ===== NOP: No Operation
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/ssr.adoc

@@ -1,4 +1,4 @@
-[id=SSR]
+[id=SSRINSTR]
 ===== SSR: Subsystem Register Read
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/ssw.adoc

@@ -1,4 +1,4 @@
-[id=SSW]
+[id=SSWINSTR]
 ===== SSW: Subsystem Register Write
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/svc.adoc

@@ -1,4 +1,4 @@
-[id=SVC]
+[id=SVCINSTR]
 ===== SVC: Supervisor Call
 [wavedrom, ,svg]
 ....