Started to document instructions and updated encoding formats (colors + added conditions)
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@ -1,48 +1,60 @@
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'rd'},
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{bits: 5, name: 'rs1'},
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{bits: 5, name: 'rs2'},
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{bits: 10, name: 'imm'}
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 5, name: 'rs2', type: 4},
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{bits: 6, name: 'imm', type: 5}
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], config: {label: {right: 'A-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'rd'},
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{bits: 5, name: 'rs1'},
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{bits: 15, name: 'imm'}
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 11, name: 'imm', type: 5}
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], config: {label: {right: 'B-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'rd'},
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{bits: 20, name: 'imm'}
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 16, name: 'imm', type: 5}
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], config: {label: {right: 'C-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode'},
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{bits: 25, name: 'imm'}
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], config: {label: {right: 'D-Type'}}}
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 21, name: 'imm', type: 5}
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], config: {label: {right: 'D1-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'reg'},
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{bits: 4, name: 'sid'},
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{bits: 8, name: 'sre'},
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{bits: 8, name: 'cmd'}
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{bits: 7, name: 'opcode', type: 8},
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{bits: 25, name: 'imm', type: 5}
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], config: {label: {right: 'D2-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 5, name: 'reg', type: 2},
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{bits: 4, name: 'sid', type: 7},
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{bits: 8, name: 'sre', type: 2},
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{bits: 8, name: 'cmd', type: 8}
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], config: {label: {right: 'E-Type'}}}
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....
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@ -7,17 +7,23 @@ For instruction encoding formats that contain an immediate value, not all immedi
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include::images/instruction-formats.adoc[]
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.Bits ranges legend
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.Format fields
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[horizontal]
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opcode::
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The operation to carry on.
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cond::
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Condition code. +
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#TODO: Define conditions encoding.#
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rd::
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Destination register.
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Destination register. +
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#TODO: Define registers encoding.#
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rs1::
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Source register 1.
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rs2::
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Source register 2.
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imm::
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Immediate value.
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Can be interpreted as signed or unsigned depending on the instruction.
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reg::
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Source/destination register on the _Execution Engine_ side.
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sid::
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@ -30,6 +36,7 @@ cmd::
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=== Instruction list
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#TODO: List instructions#
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* NOP instruction
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* memory load/store instructions
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* register move instructions
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* arithmetic instructions
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@ -39,3 +46,125 @@ cmd::
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* system mode instructions (svc, uret, sret, ...)
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* subsystems instructions (ssr & ssw)
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==== The NOP instruction
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x0, type: 8, attr: '0x0'},
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{bits: 25, name: 'unused'}
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], config: {label: {right: 'NOP'}}}
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....
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Description::
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Does nothing. Can be used to align a block of instructions.
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Encoding:: D2-Type
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Assembler syntax::
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[source]
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----
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nop
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----
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions:: None.
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==== Memory-related instructions
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===== LDR: Load Register
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x1, type: 8, attr: '0x1'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIR'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x2, type: 8, attr: '0x2'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIRW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x3, type: 8, attr: '0x3'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIOW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x4, type: 8, attr: '0x4'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDRR'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x5, type: 8, attr: '0x5'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDRRW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x6, type: 8, attr: '0x6'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDROW'}}}
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....
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====== LDRIR: Load Register Immediate Pre-indexed
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Description::
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Loads a word from memory into a register.
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The immediate offset `off` is added to the address in the `src` register before reading memory.
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Encoding:: A-Type
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Assembler syntax::
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+
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[source]
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----
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ldr{cond} dst, [src, off]
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----
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Examples::
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+
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[source]
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----
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ldr r1, [r0] ; Reads a word from the memory address in r0 into r1.
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ldr r3, [r2, 8] ; Reads a word from the memory address in r2, with a 8 bytes
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; offset, into r3.
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ldr.eq r5, [r4] ; If the last comparison resulted in an 'eq' condition status,
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; then reads a word from the memory address in r4 into r5.
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; Else, does nothing.
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----
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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[horizontal]
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MemFault:::
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If the memory address being accessed is invalid, non readable or not paged in.
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The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place.
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@ -3,6 +3,6 @@
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:icons: font
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:lang: en
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:toc: left
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:toclevels: 5
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:toclevels: 4
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:sectnums:
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:sectnumlevels: 5
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