diff --git a/src/execution-engine-spec/images/instruction-formats.adoc b/src/execution-engine-spec/images/instruction-formats.adoc index b12af0d..85769a7 100644 --- a/src/execution-engine-spec/images/instruction-formats.adoc +++ b/src/execution-engine-spec/images/instruction-formats.adoc @@ -1,48 +1,60 @@ [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 5, name: 'rs1'}, - {bits: 5, name: 'rs2'}, - {bits: 10, name: 'imm'} + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'rd', type: 2}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 5, name: 'rs2', type: 4}, + {bits: 6, name: 'imm', type: 5} ], config: {label: {right: 'A-Type'}}} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 5, name: 'rs1'}, - {bits: 15, name: 'imm'} + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'rd', type: 2}, + {bits: 5, name: 'rs1', type: 4}, + {bits: 11, name: 'imm', type: 5} ], config: {label: {right: 'B-Type'}}} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'rd'}, - {bits: 20, name: 'imm'} + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'rd', type: 2}, + {bits: 16, name: 'imm', type: 5} ], config: {label: {right: 'C-Type'}}} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode'}, - {bits: 25, name: 'imm'} -], config: {label: {right: 'D-Type'}}} + {bits: 7, name: 'opcode', type: 8}, + {bits: 4, name: 'cond', type: 6}, + {bits: 21, name: 'imm', type: 5} +], config: {label: {right: 'D1-Type'}}} .... [wavedrom, ,svg] .... {reg: [ - {bits: 7, name: 'opcode'}, - {bits: 5, name: 'reg'}, - {bits: 4, name: 'sid'}, - {bits: 8, name: 'sre'}, - {bits: 8, name: 'cmd'} + {bits: 7, name: 'opcode', type: 8}, + {bits: 25, name: 'imm', type: 5} +], config: {label: {right: 'D2-Type'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 'opcode', type: 8}, + {bits: 5, name: 'reg', type: 2}, + {bits: 4, name: 'sid', type: 7}, + {bits: 8, name: 'sre', type: 2}, + {bits: 8, name: 'cmd', type: 8} ], config: {label: {right: 'E-Type'}}} .... \ No newline at end of file diff --git a/src/execution-engine-spec/instructions.adoc b/src/execution-engine-spec/instructions.adoc index dba7b5f..6892a2e 100644 --- a/src/execution-engine-spec/instructions.adoc +++ b/src/execution-engine-spec/instructions.adoc @@ -7,17 +7,23 @@ For instruction encoding formats that contain an immediate value, not all immedi include::images/instruction-formats.adoc[] -.Bits ranges legend +.Format fields +[horizontal] opcode:: The operation to carry on. +cond:: + Condition code. + + #TODO: Define conditions encoding.# rd:: - Destination register. + Destination register. + + #TODO: Define registers encoding.# rs1:: Source register 1. rs2:: Source register 2. imm:: Immediate value. + Can be interpreted as signed or unsigned depending on the instruction. reg:: Source/destination register on the _Execution Engine_ side. sid:: @@ -30,6 +36,7 @@ cmd:: === Instruction list #TODO: List instructions# +* NOP instruction * memory load/store instructions * register move instructions * arithmetic instructions @@ -39,3 +46,125 @@ cmd:: * system mode instructions (svc, uret, sret, ...) * subsystems instructions (ssr & ssw) +==== The NOP instruction +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x0, type: 8, attr: '0x0'}, + {bits: 25, name: 'unused'} +], config: {label: {right: 'NOP'}}} +.... + +Description:: + Does nothing. Can be used to align a block of instructions. +Encoding:: D2-Type +Assembler syntax:: +[source] +---- +nop +---- +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: None. + +==== Memory-related instructions +===== LDR: Load Register +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x1, type: 8, attr: '0x1'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off', type: 5} +], config: {label: {right: 'LDRIR'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x2, type: 8, attr: '0x2'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off', type: 5} +], config: {label: {right: 'LDRIRW'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x3, type: 8, attr: '0x3'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 11, name: 'off', type: 5} +], config: {label: {right: 'LDRIOW'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x4, type: 8, attr: '0x4'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDRR'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x5, type: 8, attr: '0x5'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDRRW'}}} +.... + +[wavedrom, ,svg] +.... +{reg: [ + {bits: 7, name: 0x6, type: 8, attr: '0x6'}, + {bits: 4, name: 'cond', type: 6}, + {bits: 5, name: 'dst', type: 2}, + {bits: 5, name: 'src', type: 4}, + {bits: 5, name: 'off', type: 4}, + {bits: 6, name: 'unused'} +], config: {label: {right: 'LDROW'}}} +.... + +====== LDRIR: Load Register Immediate Pre-indexed +Description:: + Loads a word from memory into a register. + The immediate offset `off` is added to the address in the `src` register before reading memory. +Encoding:: A-Type +Assembler syntax:: ++ +[source] +---- +ldr{cond} dst, [src, off] +---- +Examples:: ++ +[source] +---- +ldr r1, [r0] ; Reads a word from the memory address in r0 into r1. +ldr r3, [r2, 8] ; Reads a word from the memory address in r2, with a 8 bytes + ; offset, into r3. +ldr.eq r5, [r4] ; If the last comparison resulted in an 'eq' condition status, + ; then reads a word from the memory address in r4 into r5. + ; Else, does nothing. +---- +Privileged instruction:: No. +Updates program state flags:: No. +Exceptions:: +[horizontal] + MemFault::: + If the memory address being accessed is invalid, non readable or not paged in. + The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place. + diff --git a/src/global-config.adoc b/src/global-config.adoc index b9463ac..ed99518 100644 --- a/src/global-config.adoc +++ b/src/global-config.adoc @@ -3,6 +3,6 @@ :icons: font :lang: en :toc: left -:toclevels: 5 +:toclevels: 4 :sectnums: :sectnumlevels: 5 \ No newline at end of file