central-arch/cmd/simtest/main.go

49 lines
1023 B
Go
Raw Normal View History

2024-11-01 10:54:59 +00:00
package main
import (
"log"
"time"
"git.elyanpoujol.fr/elyan/central-arch/pkg/breakcfg"
"git.elyanpoujol.fr/elyan/central-arch/pkg/events"
"git.elyanpoujol.fr/elyan/central-arch/pkg/sim"
"git.elyanpoujol.fr/elyan/central-arch/pkg/siminstrset"
2024-11-01 10:54:59 +00:00
)
type SysoutEventLogger struct{}
func (l *SysoutEventLogger) Log(e events.SimEvent) {
log.Printf("%v\n", e)
}
func main() {
eventLogger := &SysoutEventLogger{}
simConfig := sim.SimConfig{
RamSize: 64,
UseMMU: false,
UseCache: false,
}
schedulerConfig := sim.SchedulerConfig{BreakableEventConfig: breakcfg.New()}
breakcfg.SetSteppingType[events.CpuDecodedEvent](schedulerConfig.BreakableEventConfig, breakcfg.ALLOW_BREAK)
sim := sim.New(simConfig, schedulerConfig, eventLogger)
sim.RegisterInstructionSet(siminstrset.SimCentralInstructionSet[:])
2024-11-01 10:54:59 +00:00
/*
sim.QueueStateAccess(func(s simstate.SimState) {
s.RamState.Data[0] = 0xdeaddead
})
*/
go func() {
sim.Start()
}()
time.Sleep(5 * time.Second)
sim.Stop()
time.Sleep(time.Second)
}