2024-11-01 10:54:59 +00:00
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package main
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import (
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"fmt"
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"git.elyanpoujol.fr/elyan/central-arch/pkg/cpu"
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"git.elyanpoujol.fr/elyan/central-arch/pkg/instr"
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2024-11-03 18:38:44 +00:00
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"git.elyanpoujol.fr/elyan/central-arch/pkg/instrset"
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2024-11-01 10:54:59 +00:00
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"git.elyanpoujol.fr/elyan/central-arch/pkg/simcontext"
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2024-11-03 18:38:44 +00:00
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"git.elyanpoujol.fr/elyan/central-arch/pkg/siminstr"
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2024-11-01 10:54:59 +00:00
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)
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const (
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MOV_r1_r2 instr.Instr = 0xffff_ff2a
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SVC_ffffff instr.Instr = 0xffff_ffff
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)
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func main() {
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cpu := cpu.New(simcontext.SimContext{}, nil)
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2024-11-03 18:38:44 +00:00
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cpu.RegisterInstr(siminstr.SimInstrDesc{InstrDesc: &instrset.LDRIR, Behavior: nil})
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2024-11-01 10:54:59 +00:00
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fmt.Printf("MOV[6:0] = %#0x\n", cpu.GetOpCode(MOV_r1_r2))
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fmt.Printf("SVC[6:0] = %#0x\n", cpu.GetOpCode(SVC_ffffff))
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}
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