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No commits in common. "98ec2dd0f4ac7a3ae9bbe94e7fd23cb2c214a875" and "efe9f7da272fb8cfdd689b1c94248daa8c18ee26" have entirely different histories.

12 changed files with 289 additions and 281 deletions

View File

@ -2,11 +2,11 @@
.... ....
{reg: [ {reg: [
{bits: 7, name: 'opcode', type: 8}, {bits: 7, name: 'opcode', type: 8},
{bits: 4, name: 'imm[3:0]', type: 5}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'rd', type: 2}, {bits: 5, name: 'rd', type: 2},
{bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'rs1', type: 4},
{bits: 5, name: 'rs2', type: 4}, {bits: 5, name: 'rs2', type: 4},
{bits: 6, name: 'imm[9:4]', type: 5} {bits: 6, name: 'imm', type: 5}
], config: {label: {right: 'A1-Type'}}} ], config: {label: {right: 'A1-Type'}}}
.... ....
@ -26,10 +26,10 @@
.... ....
{reg: [ {reg: [
{bits: 7, name: 'opcode', type: 8}, {bits: 7, name: 'opcode', type: 8},
{bits: 4, name: 'imm[3:0]', type: 5}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'rd', type: 2}, {bits: 5, name: 'rd', type: 2},
{bits: 5, name: 'rs1', type: 4}, {bits: 5, name: 'rs1', type: 4},
{bits: 11, name: 'imm[14:4]', type: 5} {bits: 11, name: 'imm', type: 5}
], config: {label: {right: 'B1-Type'}}} ], config: {label: {right: 'B1-Type'}}}
.... ....
@ -48,9 +48,9 @@
.... ....
{reg: [ {reg: [
{bits: 7, name: 'opcode', type: 8}, {bits: 7, name: 'opcode', type: 8},
{bits: 4, name: 'imm[3:0]', type: 5}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'rd', type: 2}, {bits: 5, name: 'rd', type: 2},
{bits: 16, name: 'imm[19:4]', type: 5} {bits: 16, name: 'imm', type: 5}
], config: {label: {right: 'C-Type'}}} ], config: {label: {right: 'C-Type'}}}
.... ....

View File

@ -10,97 +10,97 @@
|0000~2~ |0000~2~
|0000~16~ |0000~16~
|al |AL
|Always |Always
|_None_ |_None_
|0001~2~ |0001~2~
|0001~16~ |0001~16~
|eq |EQ
|Equal |Equal
|Z==1 |Z==1
|0010~2~ |0010~2~
|0002~16~ |0002~16~
|ne |NEQ
|Not Equal |Not Equal
|Z==0 |Z==0
.2+|0011~2~ .2+|0011~2~
.2+|0003~16~ .2+|0003~16~
|ge |UGE
|Unsigned Greater or Equal |Unsigned Greater or Equal
.2+|C==1 .2+|C==1
<|cs <|CS
<|Carry Set <|Carry Set
.2+|0100~2~ .2+|0100~2~
.2+|0004~16~ .2+|0004~16~
|lt |ULT
|Unsigned Lower Than |Unsigned Lower Than
.2+|C==0 .2+|C==0
<|cc <|CC
<|Carry Clear <|Carry Clear
|0101~2~ |0101~2~
|0005~16~ |0005~16~
|neg |NEG
|Negative |Negative
|N==1 |N==1
|0110~2~ |0110~2~
|0006~16~ |0006~16~
|pos |POS
|Positive |Positive
|N==0 |N==0
|0111~2~ |0111~2~
|0007~16~ |0007~16~
|vs |VS
|oVerflow Set |oVerflow Set
|V==1 |V==1
|1000~2~ |1000~2~
|0008~16~ |0008~16~
|vc |VC
|oVerflow Clear |oVerflow Clear
|V==0 |V==0
|1001~2~ |1001~2~
|0009~16~ |0009~16~
|gt |UGT
|Unsigned Greater Than |Unsigned Greater Than
|C==1 && Z==0 |C==1 && Z==0
|1010~2~ |1010~2~
|000a~16~ |000a~16~
|le |ULE
|Unsigned Lower or Equal |Unsigned Lower or Equal
|C==0 && Z==1 |C==0 && Z==1
|1011~2~ |1011~2~
|000b~16~ |000b~16~
|sge |SGE
|Signed Greater or Equal |Signed Greater or Equal
|N==V |N==V
|1100~2~ |1100~2~
|000c~16~ |000c~16~
|slt |SLT
|Signed Lower Than |Signed Lower Than
|N!=V |N!=V
|1101~2~ |1101~2~
|000d~16~ |000d~16~
|sgt |SGT
|Signed Greater Than |Signed Greater Than
|Z==0 && N==V |Z==0 && N==V
|1110~2~ |1110~2~
|000e~16~ |000e~16~
|sle |SLE
|Signed Lower or Equal |Signed Lower or Equal
|Z==1 && N!=V |Z==1 && N!=V

View File

@ -30,10 +30,6 @@ include::instructions/svc.adoc[]
<<< <<<
==== Memory-Related Instructions ==== Memory-Related Instructions
include::instructions/ldr.adoc[] include::instructions/ldr.adoc[]
<<<
include::instructions/ldrh.adoc[]
<<<
include::instructions/ldrc.adoc[]
<<< <<<
==== Register Manipulation Instructions ==== Register Manipulation Instructions

View File

@ -33,7 +33,7 @@
====== BIO: Branch Immediate Offset ====== BIO: Branch Immediate Offset
Description:: Description::
Branch to the instruction the address of which is at `pc + off`. + Branch to the instruction the address of which is at `pc + off`. +
The assembler selects this variant over *BAIO* when a condition other than `al` is given. The assembler selects this variant over *BAIO* when a condition is given.
Encoding:: D1-Type Encoding:: D1-Type
Assembler syntax:: Assembler syntax::
+ +
@ -53,10 +53,10 @@ Examples::
+ +
[source] [source]
---- ----
b.ne -20 <1> b.al -20 <1>
b.eq 8 <2> b.eq 8 <2>
---- ----
<1> If the last comparison resulted in an 'ne' condition status, branches to `pc - 20`. Else, does nothing. <1> Branches to `pc - 20`.
<2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8`. Else, does nothing. <2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8`. Else, does nothing.
Privileged instruction:: No. Privileged instruction:: No.
@ -70,18 +70,17 @@ Exceptions::
Description:: Description::
Branch to the instruction the address of which is at `pc + off`. Branch to the instruction the address of which is at `pc + off`.
Permits the use of more bits for the offset at the cost of being unconditional. + Permits the use of more bits for the offset at the cost of being unconditional. +
The assembler selects this variant over *BIO* when no condition is given (or when `al` is given). The assembler selects this variant over *BIO* when no condition is given.
Encoding:: D2-Type Encoding:: D2-Type
Assembler syntax:: Assembler syntax::
+ +
[source] [source]
---- ----
b<cond>? <off> b <off>
---- ----
+ +
Where: Where:
[horizontal] [horizontal]
cond::: Optional condition (if specified, can only be `al`).
off::: off:::
Signed immediate offset. Signed immediate offset.
Must be in the range -8388611..8388607. Must be in the range -8388611..8388607.
@ -90,11 +89,9 @@ Examples::
+ +
[source] [source]
---- ----
b -0x3FFFFF <1> b -0x3FFFFF <1>
b.al 0x3FFFFF <2>
---- ----
<1> Branches to `pc - 0x3FFFFF`. <1> Branches to `pc - 0x3FFFFF`.
<2> Branches to `pc + 0x3FFFFF`.
Privileged instruction:: No. Privileged instruction:: No.
Updates program state flags:: No. Updates program state flags:: No.

View File

@ -61,7 +61,7 @@ Examples::
[source] [source]
---- ----
bx [r0, 12] <1> bx [r0, 12] <1>
bx.eq [r3] <2> bx.eq [r3] <2>
---- ----
<1> Branches to the instruction at address `r0 + 12`. <1> Branches to the instruction at address `r0 + 12`.
<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing. <2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3. Else, does nothing.
@ -95,7 +95,7 @@ Examples::
+ +
[source] [source]
---- ----
bx [r0, r1] <1> bx [r0, r1] <1>
bx.eq [r2, r3] <2> bx.eq [r2, r3] <2>
---- ----
<1> Branches to the instruction at address `r0 + r1`. <1> Branches to the instruction at address `r0 + r1`.

View File

@ -3,18 +3,40 @@
.... ....
{reg: [ {reg: [
{bits: 7, name: 0x1, type: 8, attr: '0x01'}, {bits: 7, name: 0x1, type: 8, attr: '0x01'},
{bits: 4, name: 'off[3:0]', type: 5}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4}, {bits: 5, name: 'src', type: 4},
{bits: 11, name: 'off[14:4]', type: 5} {bits: 11, name: 'off', type: 5}
], config: {label: {right: 'LDRI'}}} ], config: {label: {right: 'LDRIR'}}}
....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x2, type: 8, attr: '0x02'},
{bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 11, name: 'off', type: 5}
], config: {label: {right: 'LDRIRW'}}}
....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x3, type: 8, attr: '0x03'},
{bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 11, name: 'off', type: 5}
], config: {label: {right: 'LDRIOW'}}}
.... ....
[wavedrom, ,svg] [wavedrom, ,svg]
.... ....
{reg: [ {reg: [
{bits: 7, name: 0x4, type: 8, attr: '0x04'}, {bits: 7, name: 0x4, type: 8, attr: '0x04'},
{bits: 4, name: 'unused'}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4}, {bits: 5, name: 'src', type: 4},
{bits: 5, name: 'off', type: 4}, {bits: 5, name: 'off', type: 4},
@ -22,20 +44,56 @@
], config: {label: {right: 'LDRR'}}} ], config: {label: {right: 'LDRR'}}}
.... ....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x5, type: 8, attr: '0x05'},
{bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 5, name: 'off', type: 4},
{bits: 6, name: 'unused'}
], config: {label: {right: 'LDRRW'}}}
....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x6, type: 8, attr: '0x06'},
{bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 5, name: 'off', type: 4},
{bits: 6, name: 'unused'}
], config: {label: {right: 'LDROW'}}}
....
[frame=ends,grid=rows,cols="1,1"] [frame=ends,grid=rows,cols="1,1"]
|=== |===
|Instruction variant | Description |Instruction variant | Description
|LDRI |LDRIR
|<<LDRI>> |<<LDRIR>>
|LDRIRW
|<<LDRIRW>>
|LDRIOW
|<<LDRIOW>>
|LDRR |LDRR
|<<LDRR>> |<<LDRR>>
|LDRRW
|<<LDRRW>>
|LDROW
|<<LDROW>>
|=== |===
<<< <<<
[id=LDRI] [id=LDRIR]
====== LDRI: Load Register+Immediate ====== LDRIR: Load Register+Immediate Pre-indexed
Description:: Description::
Loads a word from memory into a register. Loads a word from memory into a register.
The immediate offset `off` is added to the address in the `src` register before reading memory. The immediate offset `off` is added to the address in the `src` register before reading memory.
@ -44,27 +102,112 @@ Assembler syntax::
+ +
[source] [source]
---- ----
ldr <dst>, [<src>, <off?>] ldr<cond?> <dst>, [<src>, <off?>]
---- ----
+ +
Where: Where:
[horizontal] [horizontal]
cond::: Optional condition.
dst::: Destination register. dst::: Destination register.
src::: Source register. src::: Source register.
off::: off:::
Optional offset immediate. Optional offset immediate.
Must be a multiple of 4 and in the range -65536..65532. Must be a multiple of 4 and in the range -4096..4092.
If omitted, then 0 is used. If omitted, then 0 is used.
Examples:: Examples::
+ +
[source] [source]
---- ----
ldr r1, [r0] <1> ldr r1, [r0] <1>
ldr r3, [r2, 8] <2> ldr r3, [r2, 8] <2>
ldr.eq r5, [r4] <3>
---- ----
<1> Reads a word from the memory address in r0 into r1. <1> Reads a word from the memory address in r0 into r1.
<2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3. <2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3.
<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.
<<<
[id=LDRIRW]
====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back
Description::
Increments the source register then reads a word from memory into the destination register.
The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register.
Encoding:: B1-Type
Assembler syntax::
+
[source]
----
ldr<cond?> <dst>, ![<src>, <off?>]
----
+
Where:
[horizontal]
cond::: Optional condition.
dst::: Destination register.
src::: Source register.
off:::
Optional offset immediate.
Must be a multiple of 4 and in the range -4096..4092.
If omitted, then 4 is used.
Examples::
+
[source]
----
ldr r1, ![r0] <1>
ldr r3, ![r2, 8] <2>
ldr.eq r5, ![r4] <3>
----
<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1.
<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3.
<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.
<<<
[id=LDRIOW]
====== LDRIOW: Load Register+Immediate Post-indexed with Write-back
Description::
Reads a word from memory into the destination register then increments the source register.
The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`.
Encoding:: B1-Type
Assembler syntax::
+
[source]
----
ldr<cond?> <dst>, [<src>, <off?>]!
----
+
Where:
[horizontal]
cond::: Optional condition.
dst::: Destination register.
src::: Source register.
off:::
Optional offset immediate.
Must be a multiple of 4 and in the range -4096..4092.
If omitted, then 4 is used.
Examples::
+
[source]
----
ldr r1, [r0]! <1>
ldr r3, [r2, 8]! <2>
ldr.eq r5, [r4]! <3>
----
<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4.
<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8.
<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing.
Privileged instruction:: No. Privileged instruction:: No.
Updates program state flags:: No. Updates program state flags:: No.
@ -73,7 +216,7 @@ Exceptions::
<<< <<<
[id=LDRR] [id=LDRR]
====== LDRR: Load Register+Register ====== LDRR: Load Register+Register Pre-indexed
Description:: Description::
Loads a word from memory into a register. Loads a word from memory into a register.
The value in the register `off` is added to the address in the `src` register before reading memory. The value in the register `off` is added to the address in the `src` register before reading memory.
@ -82,11 +225,12 @@ Assembler syntax::
+ +
[source] [source]
---- ----
ldr <dst>, [<src>, <off>] ldr<cond?> <dst>, [<src>, <off>]
---- ----
+ +
Where: Where:
[horizontal] [horizontal]
cond::: Optional condition.
dst::: Destination register. dst::: Destination register.
src::: Source register. src::: Source register.
off::: Offset register. off::: Offset register.
@ -95,9 +239,83 @@ Examples::
+ +
[source] [source]
---- ----
ldr r1, [sp, r0] <1> ldr r1, [sp, r0] <1>
ldr.eq r0, [r1, r2] <2>
---- ----
<1> Reads a word from the memory address in sp into r1, using the value of r0 as an offset. <1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset.
<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.
<<<
[id=LDRRW]
====== LDRRW: Load Register+Register Pre-indexed with Write-back
Description::
Increments the source register then reads a word from memory into the destination register.
The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register.
Encoding:: A1-Type
Assembler syntax::
+
[source]
----
ldr<cond?> <dst>, ![<src>, <off>]
----
+
Where:
[horizontal]
cond::: Optional condition.
dst::: Destination register.
src::: Source register.
off::: Offset register.
Examples::
+
[source]
----
ldr r1, ![sp, r0] <1>
ldr.eq r0, ![r1, r2] <2>
----
<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1.
<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.
<<<
[id=LDROW]
====== LDROW: Load Register+Register Post-indexed with Write-back
Description::
Reads a word from memory into the destination register then increments the source register.
The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`.
Encoding:: A1-Type
Assembler syntax::
+
[source]
----
ldr<cond?> <dst>, [<src>, <off>]!
----
+
Where:
[horizontal]
cond::: Optional condition.
dst::: Destination register.
src::: Source register.
off::: Offset register.
Examples::
+
[source]
----
ldr r1, [sp, r0]! <1>
ldr.eq r0, [r1, r2]! <2>
----
<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp.
<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing.
Privileged instruction:: No. Privileged instruction:: No.
Updates program state flags:: No. Updates program state flags:: No.

View File

@ -1,106 +0,0 @@
===== LDRC: Load Register Character
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x3, type: 8, attr: '0x03'},
{bits: 4, name: 'off[3:0]', type: 5},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 11, name: 'off[14:4]', type: 5}
], config: {label: {right: 'LDRCI'}}}
....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x6, type: 8, attr: '0x06'},
{bits: 4, name: 'unused'},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 5, name: 'off', type: 4},
{bits: 6, name: 'unused'}
], config: {label: {right: 'LDRCR'}}}
....
[frame=ends,grid=rows,cols="1,1"]
|===
|Instruction variant | Description
|LDRCI
|<<LDRCI>>
|LDRCR
|<<LDRCR>>
|===
<<<
[id=LDRCI]
====== LDRCI: Load Character Register+Immediate
Description::
Loads a character (or byte) from memory into a register.
The immediate offset `off` is added to the address in the `src` register before reading memory.
Encoding:: B1-Type
Assembler syntax::
+
[source]
----
ldrc <dst>, [<src>, <off?>]
----
+
Where:
[horizontal]
dst::: Destination register.
src::: Source register.
off:::
Optional offset immediate.
Must be in the range -16384..16383.
If omitted, then 0 is used.
Examples::
+
[source]
----
ldrc r1, [r0] <1>
ldrc r3, [r2, 8] <2>
----
<1> Reads a character from the memory address in r0 into r1.
<2> Reads a character from the memory address in r2, with an 8 bytes offset, into r3.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.
<<<
[id=LDRCR]
====== LDRCR: Load Character Register+Register
Description::
Loads a character (or byte) from memory into a register.
The value in the register `off` is added to the address in the `src` register before reading memory.
Encoding:: A1-Type
Assembler syntax::
+
[source]
----
ldrc <dst>, [<src>, <off>]
----
+
Where:
[horizontal]
dst::: Destination register.
src::: Source register.
off::: Offset register.
Examples::
+
[source]
----
ldrc r1, [sp, r0] <1>
----
<1> Reads a character from the memory address in sp into r1, using the value of r0 as an offset.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.

View File

@ -1,106 +0,0 @@
===== LDRH: Load Register Halfword
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x2, type: 8, attr: '0x02'},
{bits: 4, name: 'off[3:0]', type: 5},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 11, name: 'off[14:4]', type: 5}
], config: {label: {right: 'LDRHI'}}}
....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 0x5, type: 8, attr: '0x05'},
{bits: 4, name: 'unused'},
{bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4},
{bits: 5, name: 'off', type: 4},
{bits: 6, name: 'unused'}
], config: {label: {right: 'LDRHR'}}}
....
[frame=ends,grid=rows,cols="1,1"]
|===
|Instruction variant | Description
|LDRHI
|<<LDRHI>>
|LDRHR
|<<LDRHR>>
|===
<<<
[id=LDRHI]
====== LDRHI: Load Halfword Register+Immediate
Description::
Loads a halfword from memory into a register.
The immediate offset `off` is added to the address in the `src` register before reading memory.
Encoding:: B1-Type
Assembler syntax::
+
[source]
----
ldrh <dst>, [<src>, <off?>]
----
+
Where:
[horizontal]
dst::: Destination register.
src::: Source register.
off:::
Optional offset immediate.
Must be a multiple of 2 and in the range -32768..32766.
If omitted, then 0 is used.
Examples::
+
[source]
----
ldrh r1, [r0] <1>
ldrh r3, [r2, 8] <2>
----
<1> Reads a halfword from the memory address in r0 into r1.
<2> Reads a halfword from the memory address in r2, with an 8 bytes offset, into r3.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.
<<<
[id=LDRHR]
====== LDRHR: Load Halfword Register+Register
Description::
Loads a halfword from memory into a register.
The value in the register `off` is added to the address in the `src` register before reading memory.
Encoding:: A1-Type
Assembler syntax::
+
[source]
----
ldrh <dst>, [<src>, <off>]
----
+
Where:
[horizontal]
dst::: Destination register.
src::: Source register.
off::: Offset register.
Examples::
+
[source]
----
ldrh r1, [sp, r0] <1>
----
<1> Reads a halfword from the memory address in sp into r1, using the value of r0 as an offset.
Privileged instruction:: No.
Updates program state flags:: No.
Exceptions::
MemFault.

View File

@ -3,7 +3,7 @@
.... ....
{reg: [ {reg: [
{bits: 7, name: 0xd, type: 8, attr: '0x0d'}, {bits: 7, name: 0xd, type: 8, attr: '0x0d'},
{bits: 4, name: 'unused'}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'dst', type: 2},
{bits: 5, name: 'src', type: 4}, {bits: 5, name: 'src', type: 4},
{bits: 11, name: 'unused'} {bits: 11, name: 'unused'}
@ -14,9 +14,9 @@
.... ....
{reg: [ {reg: [
{bits: 7, name: 0xe, type: 8, attr: '0x0e'}, {bits: 7, name: 0xe, type: 8, attr: '0x0e'},
{bits: 4, name: 'val[3:0]', type: 5}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'dst', type: 2},
{bits: 16, name: 'val[19:4]', type: 5} {bits: 16, name: 'val', type: 5}
], config: {label: {right: 'MOVI'}}} ], config: {label: {right: 'MOVI'}}}
.... ....
@ -41,11 +41,12 @@ Assembler syntax::
+ +
[source] [source]
---- ----
mov <dst>, <src> mov<cond?> <dst>, <src>
---- ----
+ +
Where: Where:
[horizontal] [horizontal]
cond::: Optional condition.
dst::: Destination register. dst::: Destination register.
src::: Source register. src::: Source register.
@ -54,8 +55,10 @@ Examples::
[source] [source]
---- ----
mov r1, r0 <1> mov r1, r0 <1>
mov.lt r3, lr <2>
---- ----
<1> Copies the value from r0 into r1. <1> Copies the value from r0 into r1.
<2> If the last comparison resulted in an 'lt' condition status, copies the value from lr into r3. Else, does nothing.
Privileged instruction:: No. Privileged instruction:: No.
Updates program state flags:: No. Updates program state flags:: No.
@ -73,11 +76,12 @@ Assembler syntax::
+ +
[source] [source]
---- ----
mov <dst>, <val> mov<cond?> <dst>, <val>
---- ----
+ +
Where: Where:
[horizontal] [horizontal]
cond::: Optional condition.
dst::: Destination register. dst::: Destination register.
val::: Immediate value. val::: Immediate value.
@ -86,8 +90,10 @@ Examples::
[source] [source]
---- ----
mov r0, 42 <1> mov r0, 42 <1>
mov.eq r1, 1337 <2>
---- ----
<1> Sets r0 to 42. <1> Sets r0 to 42.
<2> If the last comparison resulted in an 'eq' condition status, sets r1 to 1337. Else, does nothing.
Privileged instruction:: No. Privileged instruction:: No.
Updates program state flags:: No. Updates program state flags:: No.

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@ -4,42 +4,45 @@
.... ....
{reg: [ {reg: [
{bits: 7, name: 0x13, type: 8, attr: '0x13'}, {bits: 7, name: 0x13, type: 8, attr: '0x13'},
{bits: 4, name: 'val[3:0]', type: 5}, {bits: 4, name: 'cond', type: 6},
{bits: 5, name: 'dst', type: 2}, {bits: 5, name: 'dst', type: 2},
{bits: 16, name: 'val[19:4]', type: 5} {bits: 16, name: 'val', type: 5}
], config: {label: {right: 'MOVNI'}}} ], config: {label: {right: 'MOVNI'}}}
.... ....
Description:: Description::
Sets a destination register to the implied negative value given in the immediate field. + Sets a destination register to the implied negative value given in the immediate field. +
The immediate value encoded in the instruction is a 20-bits absolute value. The immediate value encoded in the instruction is a 16-bits absolute value.
The sign bit is implied to be set, making it a 21-bits signed integer with the last bit always set. The sign bit is implied to be set, making it a 17-bits signed integer with the last bit always set.
The value is sign extended to fit in the 32-bits destination register. The value is sign extended to fit in the 32-bits destination register.
Encoding:: C-Type Encoding:: C-Type
Assembler syntax:: Assembler syntax::
+ +
[source] [source]
---- ----
movn <dst>, <val> movn<cond?> <dst>, <val>
---- ----
+ +
Where: Where:
[horizontal] [horizontal]
cond::: Optional condition.
dst::: Destination register. dst::: Destination register.
val::: val:::
Immediate value. Immediate value.
The minus sign can be omitted as the value is always negative. The minus sign can be omitted as the value is always negative.
The value must be in the range -1048576..-1. The value must be in the range -65636..-1.
Examples:: Examples::
+ +
[source] [source]
---- ----
movn r0, -42 <1> movn r0, -42 <1>
movn r0, 0x10 <2> movn r0, 0x10 <2>
movn.eq r1, -1337 <3>
---- ----
<1> Sets r0 to -42. <1> Sets r0 to -42.
<2> Sets r0 to -0x10. The minus sign is omitted but the immediate value is still treated as being negative. <2> Sets r0 to -0x10. The minus sign is omitted but the immediate value is still treated as being negative.
<3> If the last comparison resulted in an 'eq' condition status, sets r1 to -1337. Else, does nothing.
Privileged instruction:: No. Privileged instruction:: No.
Updates program state flags:: No. Updates program state flags:: No.

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@ -36,7 +36,7 @@ Examples::
+ +
[source] [source]
---- ----
ssr ss0, r1, sr0, 1 <1> ssr ss0, r1, sr0, 1 <1>
ssr ss15, pc, sr32, 0 <2> ssr ss15, pc, sr32, 0 <2>
---- ----
<1> Reads the sr0 register from the ss0 subsystem into r1 using the command _0x1_ to do so. <1> Reads the sr0 register from the ss0 subsystem into r1 using the command _0x1_ to do so.

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@ -36,7 +36,7 @@ Examples::
+ +
[source] [source]
---- ----
ssw ss0, r1, sr0, 1 <1> ssw ss0, r1, sr0, 1 <1>
ssw ss15, pc, sr32, 0 <2> ssw ss15, pc, sr32, 0 <2>
---- ----
<1> Writes the value in r1 into the sr0 register from the ss0 subsystem using the command _0x1_ to do so. <1> Writes the value in r1 into the sr0 register from the ss0 subsystem using the command _0x1_ to do so.