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07acc7ff1e
...
ea9b0f181f
@ -4,7 +4,7 @@
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[glossary]
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[horizontal]
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Processing Complex::
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Composed of a _Processing Unit_, memory modules and subsystems that are not located inside of the _Processing Unit_ (e.g. Channel I/O Subsystem, Hardware Management Subsystem).
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Composed of a _Processing Unit_, memory modules and subsystems that are not located inside of the _Processing Unit_ (e.g. Channel I/O Subsytem, Hardware Management Subsystem).
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The name applies both to the hardware enclosure and the hardware inside said enclosure.
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Processing Unit::
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@ -1,60 +1,48 @@
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 5, name: 'rs2', type: 4},
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{bits: 6, name: 'imm', type: 5}
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'rd'},
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{bits: 5, name: 'rs1'},
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{bits: 5, name: 'rs2'},
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{bits: 10, name: 'imm'}
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], config: {label: {right: 'A-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 5, name: 'rs1', type: 4},
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{bits: 11, name: 'imm', type: 5}
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'rd'},
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{bits: 5, name: 'rs1'},
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{bits: 15, name: 'imm'}
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], config: {label: {right: 'B-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'rd', type: 2},
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{bits: 16, name: 'imm', type: 5}
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'rd'},
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{bits: 20, name: 'imm'}
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], config: {label: {right: 'C-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 4, name: 'cond', type: 6},
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{bits: 21, name: 'imm', type: 5}
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], config: {label: {right: 'D1-Type'}}}
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{bits: 7, name: 'opcode'},
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{bits: 25, name: 'imm'}
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], config: {label: {right: 'D-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 25, name: 'imm', type: 5}
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], config: {label: {right: 'D2-Type'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 'opcode', type: 8},
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{bits: 5, name: 'reg', type: 2},
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{bits: 4, name: 'sid', type: 7},
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{bits: 8, name: 'sre', type: 2},
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{bits: 8, name: 'cmd', type: 8}
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{bits: 7, name: 'opcode'},
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{bits: 5, name: 'reg'},
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{bits: 4, name: 'sid'},
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{bits: 8, name: 'sre'},
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{bits: 8, name: 'cmd'}
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], config: {label: {right: 'E-Type'}}}
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....
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@ -7,23 +7,17 @@ For instruction encoding formats that contain an immediate value, not all immedi
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include::images/instruction-formats.adoc[]
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.Format fields
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[horizontal]
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.Bit ranges legend
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opcode::
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The operation to carry on.
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cond::
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Condition code. +
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#TODO: Define conditions encoding.#
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rd::
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Destination register. +
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#TODO: Define registers encoding.#
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Destination register.
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rs1::
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Source register 1.
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rs2::
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Source register 2.
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imm::
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Immediate value.
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Can be interpreted as signed or unsigned depending on the instruction.
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reg::
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Source/destination register on the _Execution Engine_ side.
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sid::
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@ -36,135 +30,3 @@ cmd::
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=== Instruction list
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#TODO: List instructions#
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* NOP instruction
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* memory load/store instructions
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* register move instructions
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* arithmetic instructions
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* bitwise operations instructions (w/ bit shifts)
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* comparison instructions
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* jump instructions
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* system mode instructions (svc, uret, sret, ...)
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* subsystems instructions (ssr & ssw)
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==== The NOP instruction
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x0, type: 8, attr: '0x0'},
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{bits: 25, name: 'unused'}
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], config: {label: {right: 'NOP'}}}
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....
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Description::
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Does nothing. Can be used to align a block of instructions.
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Encoding:: D2-Type
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Assembler syntax::
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[source]
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----
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nop
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----
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions:: None.
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==== Memory-related instructions
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===== LDR: Load Register
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x1, type: 8, attr: '0x1'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIR'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x2, type: 8, attr: '0x2'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIRW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x3, type: 8, attr: '0x3'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 11, name: 'off', type: 5}
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], config: {label: {right: 'LDRIOW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x4, type: 8, attr: '0x4'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDRR'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x5, type: 8, attr: '0x5'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDRRW'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x6, type: 8, attr: '0x6'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'dst', type: 2},
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{bits: 5, name: 'src', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'LDROW'}}}
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....
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====== LDRIR: Load Register Immediate Pre-indexed
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Description::
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Loads a word from memory into a register.
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The immediate offset `off` is added to the address in the `src` register before reading memory.
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Encoding:: A-Type
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Assembler syntax::
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+
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[source]
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----
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ldr{cond} dst, [src, off]
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----
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Examples::
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+
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[source]
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----
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ldr r1, [r0] ; Reads a word from the memory address in r0 into r1.
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ldr r3, [r2, 8] ; Reads a word from the memory address in r2, with a 8 bytes
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; offset, into r3.
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ldr.eq r5, [r4] ; If the last comparison resulted in an 'eq' condition status,
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; then reads a word from the memory address in r4 into r5.
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; Else, does nothing.
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----
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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[horizontal]
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MemFault:::
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If the memory address being accessed is invalid, non readable or not paged in.
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The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place.
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@ -7,14 +7,14 @@ The {central-arch-name} uses byte-addressable memory.
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While an _Execution engine_ handles data 32-bits wide, memory addresses are only 24-bits wide.
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An _Execution Engine_ can thus address up to 16MB of main memory.
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NOTE: We use the terms "`memory`" and "`main memory`" interchangeably. Main memory refers to the RAM while we use the term "`secondary memory`" to refer to HDD or SSD storage.
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NOTE: We use the terms "`memory`" and "`main memory`" interchangably. Main memory refers to the RAM while we use the term "`secondary memory`" to refer to HDD or SSD storage.
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At the hardware level, memory accesses are done on a memory-word boundary.
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A memory-word is 32-bits wide and memory accesses should be done at a 32-bits alignment to avoid wasting cycles doing double the amount of memory operations.
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NOTE: The term "`memory accesses`" encompasses both read and write operations.
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Data is encoded in memory in little endian.
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Data is encoded in memory with the little endian scheme.
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For a given value, the least significant byte (LSB) is stored in the lowest address and the most significant byte (MSB) in the highest.
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=== System Modes and Privilege Levels
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@ -48,7 +48,7 @@ Supervisor-mode::
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Software executing in this mode provides context switching, I/O, process management and inter-process communications.
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Fault-mode::
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Code executes in this mode when a double fault occurs, i.e. when an exception is generated in supervisor-mode code.
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Code executes in this mode when a double fault occurs, i.e. when an exception is generated in system-mode code.
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Code executing under this mode can be used to log/report double faults and then reset/halt the system.
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Debug exceptions generated in supervisor-mode code are also handled in this mode, in which case control is passed back to supervisor-mode after handling.
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@ -62,7 +62,7 @@ Exceptions thus always suspend user code for the duration of their handling.
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Exceptions can be of two types: *synchronous* and *asynchronous*.
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==== Synchronous Exceptions
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Synchronous exceptions are generated from events originating from inside of the _Execution Engine_.
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Synchronous exceptions are generated from events originating from inside of the _Execution engine_.
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They are a conditional or unconditional response to the execution of an instruction.
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SVC::
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@ -84,18 +84,11 @@ Debug::
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* Fetching an instruction located at an address matching a configured _Hardware Breakpoint_,
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* Accessing a memory address matching a configured _Hardware Watchpoint_
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SvcDebug::
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This exception is the same as the *Debug* exception, except it is generated when debug events are encountered while in supervisor-mode.
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UnknownInstr::
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This exception is generated when an unknown instruction failed to be executed.
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It is important not to ignore this exception as it can be the symptom of a memory corruption bug.
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==== Asynchronous Exceptions
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Asynchronous exceptions are generated from events originating from outside of the _Execution engine_.
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These exceptions enable the system to react to its environment.
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HdwrMgmt::
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HardMgmt::
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This exception is generated when the _Hardware Management Console_ communicates with the _Processing Unit_ and that the _Processing Unit_ relays the event to the _Execution Engine_.
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Data can be passed alongside the exception and would be stored in main memory by the _Processing Unit_ communications controller.
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@ -1,7 +1,7 @@
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=== Registers
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==== General Purpose Registers
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General purpose registers (GPRs) are used to perform calculations and store intermediate values.
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There are 8 GPRs in an _Execution Engine_. These registers are named *_r0_* through *_r7_*.
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There are 8 GPRs in an Execution Engine. These registers are named *_r0_* through *_r7_*.
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==== Special Purpose Registers
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@ -3,6 +3,6 @@
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:icons: font
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:lang: en
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:toc: left
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:toclevels: 4
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:toclevels: 5
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:sectnums:
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:sectnumlevels: 5
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Loading…
Reference in New Issue
Block a user