Added movn and clarified the use of signed offsets (+ correction of some integer ranges)

src/execution-engine-spec/instructions.adoc

@@ -5,6 +5,7 @@ Multiple instruction encoding formats are used to encode multiple kinds of instr
 The source (rs1 and rs2) and destination (rd) registers are kept at the same position in all formats to simplify decoding.
 
 For instruction encoding formats that contain an immediate value, not all immediate bits are used by all instructions sharing the format. The actual relevant bits are specified for these instructions.
+Also, immediate values are treated as unsigned unless stated otherwise.
 
 include::instruction-formats.adoc[]
 <<<
@@ -33,6 +34,8 @@ include::instructions/ldr.adoc[]
 <<<
 ==== Register Manipulation Instructions
 include::instructions/mov.adoc[]
+<<<
+include::instructions/movn.adoc[]
 
 <<<
 ==== Branching Instructions

src/execution-engine-spec/instructions/b.adoc

@@ -45,7 +45,9 @@ b<cond> <off>
 Where:
 [horizontal]
 cond::: Condition.
-off::: Immediate offset.
+off:::
+    Signed immediate offset.
+    Must be a multiple of 4 and in the range -4194304..4194300.
 
 Examples::
 +
@@ -79,7 +81,9 @@ b <off>
 +
 Where:
 [horizontal]
-off::: Immediate offset.
+off:::
+    Signed immediate offset.
+    Must be in the range -8388611..8388607.
 
 Examples::
 +

src/execution-engine-spec/instructions/bx.adoc

@@ -52,8 +52,8 @@ Where:
 cond::: Optional condition.
 base::: Base register.
 off:::
-    Optional offset immediate.
+    Optional signed offset immediate.
-    Must be a multiple of 4 and in the range 0-262140.
+    Must be a multiple of 4 and in the range -131072..131068.
     If omitted, then 0 is used.
 
 Examples::

src/execution-engine-spec/instructions/ldr.adoc

@@ -112,7 +112,7 @@ dst::: Destination register.
 src::: Source register.
 off:::
     Optional offset immediate.
-    Must be a multiple of 4 and in the range 0-8188.
+    Must be a multiple of 4 and in the range -4096..4092.
     If omitted, then 0 is used.
 
 Examples::
@@ -153,7 +153,7 @@ dst::: Destination register.
 src::: Source register.
 off:::
     Optional offset immediate.
-    Must be a multiple of 4 and in the range 0-8188.
+    Must be a multiple of 4 and in the range -4096..4092.
     If omitted, then 4 is used.
 
 Examples::
@@ -194,7 +194,7 @@ dst::: Destination register.
 src::: Source register.
 off:::
     Optional offset immediate.
-    Must be a multiple of 4 and in the range 0-8188.
+    Must be a multiple of 4 and in the range -4096..4092.
     If omitted, then 4 is used.
 
 Examples::

src/execution-engine-spec/instructions/mov.adoc

@@ -69,7 +69,8 @@ Exceptions::
 [id=MOVI]
 ====== MOVI: Move Immediate to Register
 Description::
-    Sets a destination register to the value given in the immediate field.
+    Sets a destination register to the value given in the immediate field. +
+    To set a negative value, use <<MOVNI>>.
 Encoding:: C-Type
 Assembler syntax::
 +

src/execution-engine-spec/instructions/movn.adoc

@@ -0,0 +1,51 @@
+[id=MOVNI]
+===== MOVN: Move Negative Immediate to Register
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 0x13, type: 8, attr: '0x13'},
+  {bits: 4, name: 'cond', type: 6},
+  {bits: 5,  name: 'dst', type: 2},
+  {bits: 16,  name: 'val', type: 5}
+], config: {label: {right: 'MOVNI'}}}
+....
+
+Description::
+    Sets a destination register to the implied negative value given in the immediate field. +
+    The immediate value encoded in the instruction is a 16-bits absolute value.
+    The sign bit is implied to be set, making it a 17-bits signed integer with the last bit always set.
+    The value is sign extended to fit in the 32-bits destination register.
+Encoding:: C-Type
+Assembler syntax::
++
+[source]
+----
+movn<cond?> <dst>, <val>
+----
++
+Where:
+[horizontal]
+cond::: Optional condition.
+dst::: Destination register.
+val:::
+    Immediate value.
+    The minus sign can be omitted as the value is always negative.
+    The value must be in the range -65636..-1.
+
+Examples::
++
+[source]
+----
+movn r0, -42 <1>
+movn r0, 0x10 <2>
+movn.eq r1, -1337 <3>
+----
+<1> Sets r0 to -42.
+<2> Sets r0 to -0x10. The minus sign is omitted but the immediate value is still treated as being negative.
+<3> If the last comparison resulted in an 'eq' condition status, sets r1 to -1337. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    None.
+

src/execution-engine-spec/instructions/nop.adoc

@@ -1,3 +1,4 @@
+[id=NOP]
 ===== NOP: No Operation
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/ssr.adoc

@@ -1,3 +1,4 @@
+[id=SSR]
 ===== SSR: Subsystem Register Read
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/ssw.adoc

@@ -1,3 +1,4 @@
+[id=SSW]
 ===== SSW: Subsystem Register Write
 [wavedrom, ,svg]
 ....

src/execution-engine-spec/instructions/svc.adoc

@@ -1,3 +1,4 @@
+[id=SVC]
 ===== SVC: Supervisor Call
 [wavedrom, ,svg]
 ....