Added conditions and registers encodings in instruction formats

src/execution-engine-spec/instructions-operands-encoding.adoc

@@ -0,0 +1,194 @@
+[id=conditions-encoding]
+==== Conditions Encoding
+
+[%header,cols="^1,^1,1,2,2"]
+|===
+2+|Value
+^|Name
+^|Description
+^|Flags
+
+|0000~2~
+|0000~16~
+|AL
+|Always
+|_None_
+
+|0001~2~
+|0001~16~
+|EQ
+|Equal
+|Z==1
+
+|0010~2~
+|0002~16~
+|NEQ
+|Not Equal
+|Z==0
+
+.2+|0011~2~
+.2+|0003~16~
+|UGE
+|Unsigned Greater or Equal
+.2+|C==1
+
+<|CS
+<|Carry Set
+
+.2+|0100~2~
+.2+|0004~16~
+|ULT
+|Unsigned Lower Than
+.2+|C==0
+
+<|CC
+<|Carry Clear
+
+|0101~2~
+|0005~16~
+|NEG
+|Negative
+|N==1
+
+|0110~2~
+|0006~16~
+|POS
+|Positive
+|N==0
+
+|0111~2~
+|0007~16~
+|VS
+|oVerflow Set
+|V==1
+
+|1000~2~
+|0008~16~
+|VC
+|oVerflow Clear
+|V==0
+
+|1001~2~
+|0009~16~
+|UGT
+|Unsigned Greater Than
+|C==1 && Z==0
+
+|1010~2~
+|000a~16~
+|ULE
+|Unsigned Lower or Equal
+|C==0 && Z==1
+
+|1011~2~
+|000b~16~
+|SGE
+|Signed Greater or Equal
+|N==V
+
+|1100~2~
+|000c~16~
+|SLT
+|Signed Lower Than
+|N!=V
+
+|1101~2~
+|000d~16~
+|SGT
+|Signed Greater Than
+|Z==0 && N==V
+
+|1110~2~
+|000e~16~
+|SLE
+|Signed Lower or Equal
+|Z==1 && N!=V
+
+|1111~2~
+|000f~16~
+|_N/A_
+|_Unspecified, reserved for future use_
+|_N/A_
+|===
+
+[id=registers-encoding]
+==== Registers Encoding
+
+[%header,cols="^1,^1,2"]
+|===
+2+|Value
+|Name
+
+|00000~2~
+|00000~16~
+|r0
+
+|00001~2~
+|00001~16~
+|r1
+
+|00010~2~
+|00002~16~
+|r2
+
+|00011~2~
+|00003~16~
+|r3
+
+|00100~2~
+|00004~16~
+|r4
+
+|00101~2~
+|00005~16~
+|r5
+
+|00110~2~
+|00006~16~
+|r6
+
+|00111~2~
+|00007~16~
+|r7
+
+|01000~2~ .. 10110~2~
+|00008~16~ .. 00016~16~
+|_Reserved_
+
+|10111~2~
+|00017~16~
+|lr
+
+|11000~2~
+|00018~16~
+|pc
+
+|11001~2~
+|00019~16~
+|sp
+
+|11010~2~
+|0001a~16~
+|pc_user
+
+|11011~2~
+|0001b~16~
+|sp_user
+
+|11100~2~
+|0001c~16~
+|pc_svc
+
+|11101~2~
+|0001d~16~
+|sp_svc
+
+|11110~2~
+|0001e~16~
+|pc_fault
+
+|11111~2~
+|0001f~16~
+|sp_fault
+|===
+

src/execution-engine-spec/instructions.adoc

@@ -1,5 +1,6 @@
 == Instructions
-=== Instruction Encoding Formats
+=== Instruction Encoding
+==== Instruction Formats
 Multiple instruction encoding formats are used to encode multiple kinds of instructions.
 The source (rs1 and rs2) and destination (rd) registers are kept at the same position in all formats to simplify decoding.
 
@@ -13,10 +14,10 @@ opcode::
     The operation to carry on.
 cond::
     Condition code. +
-    #TODO: Define conditions encoding.#
+    See <<conditions-encoding>>.
 rd::
     Destination register. +
-    #TODO: Define registers encoding.#
+    See <<registers-encoding>>.
 rs1::
     Source register 1.
 rs2::
@@ -33,6 +34,8 @@ sre::
 cmd::
     Subsystem command.
 
+include::instructions-operands-encoding.adoc[]
+
 <<<
 === Instruction list
 #TODO: List instructions#