Added EE modes and registers + enhanced layout
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@ -7,7 +7,7 @@ This document presents the public interface of an _Execution Engine_ of the {cen
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This means that the amount of information pertaining to the internals of an _Execution Engine_ hardware implementation are kept at a minimum except when a choice in the public interface is specifically made to simplify said implementation.
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This means that the amount of information pertaining to the internals of an _Execution Engine_ hardware implementation are kept at a minimum except when a choice in the public interface is specifically made to simplify said implementation.
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include::execution-engine-spec/glossary.adoc[]
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include::execution-engine-spec/glossary.adoc[]
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include::execution-engine-spec/data-manipulation.adoc[]
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include::execution-engine-spec/data-manipulation.adoc[]
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include::execution-engine-spec/ee-modes.adoc[]
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include::execution-engine-spec/registers.adoc[]
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include::execution-engine-spec/instructions.adoc[]
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include::execution-engine-spec/instructions.adoc[]
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== Data Manipulation
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== Data Manipulation
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=== Data width
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=== Data Width
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All the registers of the {central-arch-name} are 32bit wide.
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All the registers of the {central-arch-name} are 32bit wide.
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=== Address width
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=== Address Width
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Memory addresses are 24bit wide thus an _Execution Engine_ can address up to 16MB of memory.
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Memory addresses are 24bit wide thus an _Execution Engine_ can address up to 16MB of memory.
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=== Memory alignment
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=== Memory Alignment
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The {central-arch-name} uses byte-addressable memory. Under the hood, memory accesses are done on a memory-word boundary.
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The {central-arch-name} uses byte-addressable memory. Under the hood, memory accesses are done on a memory-word boundary.
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A memory-word is 32bit wide. To maximize performance, memory accesses should be done on a 32bit alignment.
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A memory-word is 32bit wide. To maximize performance, memory accesses should be done on a 32bit alignment.
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NOTE: The term "`memory accesses`" encompasses both read and write operations.
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NOTE: The term "`memory accesses`" encompasses both read and write operations.
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=== Endianness
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=== Endianness
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Data is encoded in memory with the little endian scheme. For a given value, the least significant byte (LSB) is stored in the lowest address and the most significant byte (MSB) in the highest.
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Data is encoded in memory with the little endian scheme. For a given value, the least significant byte (LSB) is stored in the lowest address and the most significant byte (MSB) in the highest.
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11
src/execution-engine-spec/ee-modes.adoc
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11
src/execution-engine-spec/ee-modes.adoc
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== Execution Engine Modes
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User-mode::
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Lowest privilege level. User programs execute in this mode. These programs can access services provided in a higher privilege level by making supervisor calls (SVCs).
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System-mode::
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Highest privilege level (on par with fault-mode). The kernel executes its code in this mode. Control is passed to code executing in this mode when exceptions occur or when a user program makes a supervisor call (SVC).
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Fault-mode::
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Code only executes in this mode when a double fault occurs, i.e. when an exception is generated in system-mode code. The code executing under this mode should do the bare minimum to log or report the error and then reset/halt the system.
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@ -3,4 +3,5 @@
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[glossary]
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[glossary]
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Central Processing Unit:: An hardware unit containing one or more _Execution Engines_, a memory controller, an interrupt controller, an operator facility controller and various other minor components.
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Central Processing Unit:: An hardware unit containing one or more _Execution Engines_, a memory controller, an interrupt controller, an operator facility controller and various other minor components.
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Execution Engine:: The hardware responsible for the execution of user-written code, be it kernel code or user program code. An _Execution Engine_ contains a fetch unit, a decode unit, a micro-instruction sequencer, an Arithmetic & Logic Unit, various registers and subsystems. An _Execution Engine_ is analogous to an _hart_ in the RISC-V nomenclature or to a _core_ in other CPU specifications.
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Execution Engine:: The hardware responsible for the execution of user-written code, be it kernel code or user program code. An _Execution Engine_ contains a fetch unit, a decode unit, a micro-instruction sequencer, an Arithmetic & Logic Unit, various registers and subsystems. An _Execution Engine_ is analogous to an _hart_ in the RISC-V nomenclature or to a _core_ in other CPU specifications.
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68
src/execution-engine-spec/registers.adoc
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src/execution-engine-spec/registers.adoc
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== Registers
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=== General Purpose Registers
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General purpose registers (GPRs) are used to perform calculations and store intermediate values. There are 8 GPRs in an Execution Engine. These registers are named *_r0_* through *_r7_*.
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=== Special Purpose Registers
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[cols="1,1,1,1,3"]
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|===
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|Name |User-mode |Supervisor-mode |Fault-mode |Description
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|lr
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|X
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|X
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|X
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|Link register. Store the return address from a Branch-with-Link.
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|pc
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|X
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|X
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|X
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|Program counter alias register. It is used as an alias to the current processor mode program counter register.
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|sp
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|X
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|X
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|X
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|Stack pointer alias register. It is used as an alias to the current processor mode stack pointer register.
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|pc_user
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|X
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|X
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|X
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|User-mode program counter.
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|sp_user
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|X
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|X
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|X
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|User-mode stack pointer.
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|pc_sys
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|X
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|X
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|Supervisor-mode program counter.
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|sp_sys
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|X
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|X
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|Supervisor-mode stack pointer.
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|pc_fault
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|X
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|X
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|Fault-mode program counter.
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|sp_fault
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|X
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|X
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|Fault-mode stack pointer.
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|===
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#Add a Program Status Register (ALU flags C, Z, N, V and processor modes U, S, F), an Exception Status Register and a Channel Status Register. --> Or do we put it in subsystems?#
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@ -3,4 +3,6 @@
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:icons: font
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:icons: font
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:lang: en
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:lang: en
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:toc: left
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:toc: left
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:toclevels: 5
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:toclevels: 5
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:sectnums:
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:sectnumlevels: 5
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