Added EE modes and registers + enhanced layout
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Elyan 2024-10-13 23:40:56 +02:00
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@ -7,7 +7,7 @@ This document presents the public interface of an _Execution Engine_ of the {cen
This means that the amount of information pertaining to the internals of an _Execution Engine_ hardware implementation are kept at a minimum except when a choice in the public interface is specifically made to simplify said implementation. This means that the amount of information pertaining to the internals of an _Execution Engine_ hardware implementation are kept at a minimum except when a choice in the public interface is specifically made to simplify said implementation.
include::execution-engine-spec/glossary.adoc[] include::execution-engine-spec/glossary.adoc[]
include::execution-engine-spec/data-manipulation.adoc[] include::execution-engine-spec/data-manipulation.adoc[]
include::execution-engine-spec/ee-modes.adoc[]
include::execution-engine-spec/registers.adoc[]
include::execution-engine-spec/instructions.adoc[] include::execution-engine-spec/instructions.adoc[]

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== Data Manipulation == Data Manipulation
=== Data width === Data Width
All the registers of the {central-arch-name} are 32bit wide. All the registers of the {central-arch-name} are 32bit wide.
=== Address width === Address Width
Memory addresses are 24bit wide thus an _Execution Engine_ can address up to 16MB of memory. Memory addresses are 24bit wide thus an _Execution Engine_ can address up to 16MB of memory.
=== Memory alignment === Memory Alignment
The {central-arch-name} uses byte-addressable memory. Under the hood, memory accesses are done on a memory-word boundary. The {central-arch-name} uses byte-addressable memory. Under the hood, memory accesses are done on a memory-word boundary.
A memory-word is 32bit wide. To maximize performance, memory accesses should be done on a 32bit alignment. A memory-word is 32bit wide. To maximize performance, memory accesses should be done on a 32bit alignment.
@ -13,3 +13,4 @@ NOTE: The term "`memory accesses`" encompasses both read and write operations.
=== Endianness === Endianness
Data is encoded in memory with the little endian scheme. For a given value, the least significant byte (LSB) is stored in the lowest address and the most significant byte (MSB) in the highest. Data is encoded in memory with the little endian scheme. For a given value, the least significant byte (LSB) is stored in the lowest address and the most significant byte (MSB) in the highest.

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== Execution Engine Modes
User-mode::
Lowest privilege level. User programs execute in this mode. These programs can access services provided in a higher privilege level by making supervisor calls (SVCs).
System-mode::
Highest privilege level (on par with fault-mode). The kernel executes its code in this mode. Control is passed to code executing in this mode when exceptions occur or when a user program makes a supervisor call (SVC).
Fault-mode::
Code only executes in this mode when a double fault occurs, i.e. when an exception is generated in system-mode code. The code executing under this mode should do the bare minimum to log or report the error and then reset/halt the system.

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[glossary] [glossary]
Central Processing Unit:: An hardware unit containing one or more _Execution Engines_, a memory controller, an interrupt controller, an operator facility controller and various other minor components. Central Processing Unit:: An hardware unit containing one or more _Execution Engines_, a memory controller, an interrupt controller, an operator facility controller and various other minor components.
Execution Engine:: The hardware responsible for the execution of user-written code, be it kernel code or user program code. An _Execution Engine_ contains a fetch unit, a decode unit, a micro-instruction sequencer, an Arithmetic & Logic Unit, various registers and subsystems. An _Execution Engine_ is analogous to an _hart_ in the RISC-V nomenclature or to a _core_ in other CPU specifications. Execution Engine:: The hardware responsible for the execution of user-written code, be it kernel code or user program code. An _Execution Engine_ contains a fetch unit, a decode unit, a micro-instruction sequencer, an Arithmetic & Logic Unit, various registers and subsystems. An _Execution Engine_ is analogous to an _hart_ in the RISC-V nomenclature or to a _core_ in other CPU specifications.

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== Registers
=== General Purpose Registers
General purpose registers (GPRs) are used to perform calculations and store intermediate values. There are 8 GPRs in an Execution Engine. These registers are named *_r0_* through *_r7_*.
=== Special Purpose Registers
[cols="1,1,1,1,3"]
|===
|Name |User-mode |Supervisor-mode |Fault-mode |Description
|lr
|X
|X
|X
|Link register. Store the return address from a Branch-with-Link.
|pc
|X
|X
|X
|Program counter alias register. It is used as an alias to the current processor mode program counter register.
|sp
|X
|X
|X
|Stack pointer alias register. It is used as an alias to the current processor mode stack pointer register.
|pc_user
|X
|X
|X
|User-mode program counter.
|sp_user
|X
|X
|X
|User-mode stack pointer.
|pc_sys
|
|X
|X
|Supervisor-mode program counter.
|sp_sys
|
|X
|X
|Supervisor-mode stack pointer.
|pc_fault
|
|X
|X
|Fault-mode program counter.
|sp_fault
|
|X
|X
|Fault-mode stack pointer.
|===
#Add a Program Status Register (ALU flags C, Z, N, V and processor modes U, S, F), an Exception Status Register and a Channel Status Register. --> Or do we put it in subsystems?#

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:lang: en :lang: en
:toc: left :toc: left
:toclevels: 5 :toclevels: 5
:sectnums:
:sectnumlevels: 5