Added bl and blx instructions
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@ -46,6 +46,10 @@ include::instructions/movn.adoc[]
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include::instructions/b.adoc[]
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<<<
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include::instructions/bx.adoc[]
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<<<
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include::instructions/bl.adoc[]
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<<<
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include::instructions/blx.adoc[]
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<<<
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==== Subsystems Instructions
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103
src/execution-engine-spec/instructions/bl.adoc
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103
src/execution-engine-spec/instructions/bl.adoc
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@ -0,0 +1,103 @@
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===== BL: Branch with Link
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x14, type: 8, attr: '0x14'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 21, name: 'off', type: 5}
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], config: {label: {right: 'BLIO'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x15, type: 8, attr: '0x15'},
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{bits: 1, name: 0},
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{bits: 24, name: 'off', type: 5}
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], config: {label: {right: 'BLAIO'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|BLIO
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|<<BLIO>>
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|BLAIO
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|<<BLAIO>>
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|===
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<<<
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[id=BLIO]
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====== BLIO: Branch with Link Immediate Offset
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Description::
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Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `pc + off`. +
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The assembler selects this variant over *BLAIO* when a condition other than `al` is given.
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Encoding:: D1-Type
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Assembler syntax::
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+
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[source]
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----
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bl<cond> <off>
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----
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+
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Where:
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[horizontal]
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cond::: Condition.
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off:::
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Signed immediate offset.
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Must be a multiple of 4 and in the range -4194304..4194300.
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Examples::
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+
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[source]
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----
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bl.ne -20 <1>
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bl.eq 8 <2>
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----
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<1> If the last comparison resulted in an 'ne' condition status, branches to `pc - 20` after storing `pc + 4` into *lr*. Else, does nothing.
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<2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8` after storing `pc + 4` into *lr*. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=BLAIO]
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====== BLAIO: Branch with Link Always Immediate Offset
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Description::
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Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `pc + off`.
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Permits the use of more bits for the offset at the cost of being unconditional. +
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The assembler selects this variant over *BLIO* when no condition is given (or when `al` is given).
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Encoding:: D2-Type
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Assembler syntax::
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+
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[source]
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----
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bl<cond>? <off>
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition (if specified, can only be `al`).
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off:::
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Signed immediate offset.
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Must be in the range -8388611..8388607.
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Examples::
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+
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[source]
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----
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bl -0x3FFFFF <1>
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bl.al 0x3FFFFF <2>
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----
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<1> Branches to `pc - 0x3FFFFF` after storing `pc + 4` into *lr*.
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<2> Branches to `pc + 0x3FFFFF` after storing `pc + 4` into *lr*.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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108
src/execution-engine-spec/instructions/blx.adoc
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108
src/execution-engine-spec/instructions/blx.adoc
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@ -0,0 +1,108 @@
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===== BLX: Branch with Link Extended
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x16, type: 8, attr: '0x16'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'off[4:0]', type: 5},
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{bits: 5, name: 'base', type: 4},
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{bits: 11, name: 'off[15:5]', type: 5}
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], config: {label: {right: 'BLXI'}}}
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....
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[wavedrom, ,svg]
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....
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{reg: [
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{bits: 7, name: 0x17, type: 8, attr: '0x17'},
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{bits: 4, name: 'cond', type: 6},
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{bits: 5, name: 'unused'},
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{bits: 5, name: 'base', type: 4},
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{bits: 5, name: 'off', type: 4},
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{bits: 6, name: 'unused'}
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], config: {label: {right: 'BLXR'}}}
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....
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[frame=ends,grid=rows,cols="1,1"]
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|===
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|Instruction variant | Description
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|BLXI
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|<<BLXI>>
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|BLXR
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|<<BLXR>>
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|===
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<<<
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[id=BLXI]
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====== BLXI: Branch with Link Extended Immediate
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Description::
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Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `base + off`.
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Permits to use a varying base address with a fixed offset.
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Encoding:: B2-Type
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Assembler syntax::
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+
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[source]
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----
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blx<cond?> [<base>, <off?>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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base::: Base register.
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off:::
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Optional signed offset immediate.
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Must be a multiple of 4 and in the range -131072..131068.
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If omitted, then 0 is used.
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Examples::
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+
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[source]
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----
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blx [r0, 12] <1>
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blx.eq [r3] <2>
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----
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<1> Branches to the instruction at address `r0 + 12` after storing `pc + 4` into *lr*.
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<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3 after storing `pc + 4` into *lr*. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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<<<
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[id=BLXR]
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====== BLXR: Branch with Link Extended Register
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Description::
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Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `base + off`.
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Permits to use a varying base address with a varying offset.
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Encoding:: A2-Type
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Assembler syntax::
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+
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[source]
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----
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blx<cond?> [<base>, <off>]
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----
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+
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Where:
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[horizontal]
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cond::: Optional condition.
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base::: Base register.
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off::: Offset register.
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Examples::
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+
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[source]
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----
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blx [r0, r1] <1>
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blx.eq [r2, r3] <2>
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----
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<1> Branches to the instruction at address `r0 + r1` after storing `pc + 4` into *lr*.
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<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3` after storing `pc + 4` into *lr*. Else, does nothing.
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Privileged instruction:: No.
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Updates program state flags:: No.
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Exceptions::
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MemFault.
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