Added bl and blx instructions

src/execution-engine-spec/instructions.adoc

@@ -46,6 +46,10 @@ include::instructions/movn.adoc[]
 include::instructions/b.adoc[]
 <<<
 include::instructions/bx.adoc[]
+<<<
+include::instructions/bl.adoc[]
+<<<
+include::instructions/blx.adoc[]
 
 <<<
 ==== Subsystems Instructions

src/execution-engine-spec/instructions/bl.adoc

@@ -0,0 +1,103 @@
+===== BL: Branch with Link
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 0x14, type: 8, attr: '0x14'},
+  {bits: 4, name: 'cond', type: 6},
+  {bits: 21, name: 'off', type: 5}
+], config: {label: {right: 'BLIO'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 0x15, type: 8, attr: '0x15'},
+  {bits: 1, name: 0},
+  {bits: 24, name: 'off', type: 5}
+], config: {label: {right: 'BLAIO'}}}
+....
+
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction variant | Description
+
+|BLIO
+|<<BLIO>>
+
+|BLAIO
+|<<BLAIO>>
+|===
+
+<<<
+[id=BLIO]
+====== BLIO: Branch with Link Immediate Offset
+Description::
+    Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `pc + off`. +
+    The assembler selects this variant over *BLAIO* when a condition other than `al` is given.
+Encoding:: D1-Type
+Assembler syntax::
++
+[source]
+----
+bl<cond> <off>
+----
++
+Where:
+[horizontal]
+cond::: Condition.
+off:::
+    Signed immediate offset.
+    Must be a multiple of 4 and in the range -4194304..4194300.
+
+Examples::
++
+[source]
+----
+bl.ne -20 <1>
+bl.eq 8   <2>
+----
+<1> If the last comparison resulted in an 'ne' condition status, branches to `pc - 20` after storing `pc + 4` into *lr*. Else, does nothing.
+<2> If the last comparison resulted in an 'eq' condition status, branches to `pc + 8` after storing `pc + 4` into *lr*. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
+
+<<<
+[id=BLAIO]
+====== BLAIO: Branch with Link Always Immediate Offset
+Description::
+    Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `pc + off`.
+    Permits the use of more bits for the offset at the cost of being unconditional. +
+    The assembler selects this variant over *BLIO* when no condition is given (or when `al` is given).
+Encoding:: D2-Type
+Assembler syntax::
++
+[source]
+----
+bl<cond>? <off>
+----
++
+Where:
+[horizontal]
+cond::: Optional condition (if specified, can only be `al`).
+off:::
+    Signed immediate offset.
+    Must be in the range -8388611..8388607.
+
+Examples::
++
+[source]
+----
+bl -0x3FFFFF   <1>
+bl.al 0x3FFFFF <2>
+----
+<1> Branches to `pc - 0x3FFFFF` after storing `pc + 4` into *lr*.
+<2> Branches to `pc + 0x3FFFFF` after storing `pc + 4` into *lr*.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
+

src/execution-engine-spec/instructions/blx.adoc

@@ -0,0 +1,108 @@
+===== BLX: Branch with Link Extended
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 0x16, type: 8, attr: '0x16'},
+  {bits: 4, name: 'cond', type: 6},
+  {bits: 5,  name: 'off[4:0]', type: 5},
+  {bits: 5,  name: 'base', type: 4},
+  {bits: 11,  name: 'off[15:5]', type: 5}
+], config: {label: {right: 'BLXI'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 0x17, type: 8, attr: '0x17'},
+  {bits: 4, name: 'cond', type: 6},
+  {bits: 5,  name: 'unused'},
+  {bits: 5,  name: 'base', type: 4},
+  {bits: 5,  name: 'off', type: 4},
+  {bits: 6,  name: 'unused'}
+], config: {label: {right: 'BLXR'}}}
+....
+
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction variant | Description
+
+|BLXI
+|<<BLXI>>
+
+|BLXR
+|<<BLXR>>
+|===
+
+<<<
+[id=BLXI]
+====== BLXI: Branch with Link Extended Immediate
+Description::
+    Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `base + off`.
+    Permits to use a varying base address with a fixed offset.
+Encoding:: B2-Type
+Assembler syntax::
++
+[source]
+----
+blx<cond?> [<base>, <off?>]
+----
++
+Where:
+[horizontal]
+cond::: Optional condition.
+base::: Base register.
+off:::
+    Optional signed offset immediate.
+    Must be a multiple of 4 and in the range -131072..131068.
+    If omitted, then 0 is used.
+
+Examples::
++
+[source]
+----
+blx [r0, 12] <1>
+blx.eq [r3]  <2>
+----
+<1> Branches to the instruction at address `r0 + 12` after storing `pc + 4` into *lr*.
+<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at the address in r3 after storing `pc + 4` into *lr*. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
+
+<<<
+[id=BLXR]
+====== BLXR: Branch with Link Extended Register
+Description::
+    Stores the value of `pc + 4` into *lr* then branch to the instruction the address of which is at `base + off`.
+    Permits to use a varying base address with a varying offset.
+Encoding:: A2-Type
+Assembler syntax::
++
+[source]
+----
+blx<cond?> [<base>, <off>]
+----
++
+Where:
+[horizontal]
+cond::: Optional condition.
+base::: Base register.
+off::: Offset register.
+
+Examples::
++
+[source]
+----
+blx [r0, r1]    <1>
+blx.eq [r2, r3] <2>
+----
+<1> Branches to the instruction at address `r0 + r1` after storing `pc + 4` into *lr*.
+<2> If the last comparison resulted in an 'eq' condition status, branches to the instruction at address `r2 + r3` after storing `pc + 4` into *lr*. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
+