Created a proper intro and refactored the doc
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@ -7,7 +7,6 @@ This document presents the public interface of an _Execution Engine_ of the {cen
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This means that the amount of information pertaining to the internals of an _Execution Engine_ hardware implementation are kept at a minimum except when a choice in the public interface is specifically made to simplify said implementation.
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include::execution-engine-spec/glossary.adoc[]
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include::execution-engine-spec/data-manipulation.adoc[]
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include::execution-engine-spec/ee-modes.adoc[]
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include::execution-engine-spec/intro.adoc[]
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include::execution-engine-spec/registers.adoc[]
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include::execution-engine-spec/instructions.adoc[]
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== Data Manipulation
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=== Data Width
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All the registers of the {central-arch-name} are 32bit wide.
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=== Address Width
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Memory addresses are 24bit wide thus an _Execution Engine_ can address up to 16MB of memory.
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=== Memory Alignment
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The {central-arch-name} uses byte-addressable memory. Under the hood, memory accesses are done on a memory-word boundary.
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A memory-word is 32bit wide. To maximize performance, memory accesses should be done on a 32bit alignment.
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NOTE: The term "`memory accesses`" encompasses both read and write operations.
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=== Endianness
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Data is encoded in memory with the little endian scheme. For a given value, the least significant byte (LSB) is stored in the lowest address and the most significant byte (MSB) in the highest.
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== Execution Engine Modes
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User-mode::
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Lowest privilege level. User programs execute in this mode. These programs can access services provided in a higher privilege level by making supervisor calls (SVCs).
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System-mode::
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Highest privilege level (on par with fault-mode). The kernel executes its code in this mode. Control is passed to code executing in this mode when exceptions occur or when a user program makes a supervisor call (SVC).
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Fault-mode::
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Code only executes in this mode when a double fault occurs, i.e. when an exception is generated in system-mode code. The code executing under this mode should do the bare minimum to log or report the error and then reset/halt the system.
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== Glossary
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[glossary]
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Central Processing Unit:: An hardware unit containing one or more _Execution Engines_, a memory controller, an interrupt controller, an operator facility controller and various other minor components.
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Execution Engine:: The hardware responsible for the execution of user-written code, be it kernel code or user program code. An _Execution Engine_ contains a fetch unit, a decode unit, a micro-instruction sequencer, an Arithmetic & Logic Unit, various registers and subsystems. An _Execution Engine_ is analogous to an _hart_ in the RISC-V nomenclature or to a _core_ in other CPU specifications.
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[horizontal]
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Processing Complex::
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The hardware enclosure and the hardware inside said enclosure.
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Composed of _Processing Units_, memory modules & controllers, an I/O subsystem, an _HMC_ communications controller and various other components.
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Processing Unit::
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An hardware unit containing one or more _Execution Engines_, cache controllers, an interrupt controller, ...
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Execution Engine::
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The hardware responsible for the execution of user-written code, be it kernel code or user program code.
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An _Execution Engine_ contains a fetch unit, a decode unit, a micro-instruction sequencer, an Arithmetic & Logic Unit, various registers and subsystems.
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An _Execution Engine_ is analogous to an _hart_ in a RISC-V processor or to a _core_ in other CPU specifications.
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HMC::
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Stands for Hardware Management Console.
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This is a console directly attached to the _Processor Complex_ that is used to manage the different aspects of the hardware.
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For example, the HMC is reponsible for loading the _Boot Code_ into main memory and instructing the _Processing Units_ to begin executing code at a given address.
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== Instructions
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=== Instruction Encoding Formats
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Multiple instruction encoding formats are used to encode multiple kinds of instructions.
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The source (rs1 and rs2) and destination (rd) registers are kept at the same position in all formats to simplify decoding.
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include::images/instruction-formats.adoc[]
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include::images/instruction-formats.adoc[]
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src/execution-engine-spec/intro.adoc
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src/execution-engine-spec/intro.adoc
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== Introduction
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=== Overview
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The {central-arch-name} is a 32-bits architecture meaning that most of the registers present in an _execution engine_ are 32-bits wide.
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=== Memory
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The {central-arch-name} uses byte-addressable memory.
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While an _execution engine_ handles data 32-bits wide, memory addresses are only 24-bits wide.
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An _Execution Engine_ can thus address up to 16MB of main memory.
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NOTE: We use the terms "`memory`" and "`main memory`" interchangably. Main memory refers to the RAM while we use the term "`secondary memory`" to refer to HDD or SSD storage.
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At the hardware level, memory accesses are done on a memory-word boundary.
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A memory-word is 32-bits wide and memory accesses should be done at a 32-bits alignment to avoid wasting cycles doing double the amount of memory operations.
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NOTE: The term "`memory accesses`" encompasses both read and write operations.
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Data is encoded in memory with the little endian scheme.
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For a given value, the least significant byte (LSB) is stored in the lowest address and the most significant byte (MSB) in the highest.
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=== System modes and privilege levels
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There are three system modes divided into two privilege levels.
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The privilege levels are `privileged` and `unprivileged`.
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Some instructions can only be executed and some registers can only be accessed while running under a system mode belonging to the `privileged` privilege level.
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.System modes
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[cols="1,1"]
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|===
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|Name |Privilege level
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|User-mode
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|Unprivileged
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|Supervisor-mode
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|Privileged
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|Fault-mode
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|Privileged
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|===
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User-mode::
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User programs execute in this mode.
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These programs can access services provided in a higher privilege level by making supervisor calls (SVCs).
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Supervisor-mode::
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The kernel executes its code in this mode.
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Control is passed to code executing in this mode when exceptions occur.
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Software executing in this mode provides context switching, I/O, process management and inter-process communications.
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Fault-mode::
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Code executes in this mode when a double fault occurs, i.e. when an exception is generated in system-mode code.
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Code executing under this mode can be used to log/report double faults and then reset/halt the system.
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Debug exceptions generated in supervisor-mode code are also handled in this mode, in which case control is passed back to supervisor-mode after handling.
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=== Exceptions
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Exceptions are events that need to be acknowledged and handled by the system.
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Exceptions change the state of the _execution engine_ so that privileged software can be executed to handle them.
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Exceptions thus always suspend user code for the duration of their handling.
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Exceptions can be of two types: *synchronous* and *asynchronous*.
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==== Synchronous exceptions
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Synchronous exceptions are generated from inside an _execution engine_.
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They are a conditional or unconditional response to the execution of an instruction.
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SVC::
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Supervisor call exceptions are generated when a user program calls the `svc` instruction.
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Supervisor calls are used to perform privileged actions in a secure manner.
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DataFault::
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A data fault is generated when an instruction references a memory address that is not mapped in virtual memory or that does not exist.
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This exception is generated when read or writing memory as well as fetching an instruction.
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SysTick::
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This exception is generated each time a system programed timer ticks at regular intervals.
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This exception is used to implement context switching.
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Debug::
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TODO
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==== Asynchronous exceptions
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Asynchronous exceptions are generated from outside an _execution engine_.
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These exceptions enable the system to react to its environment.
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HMC::
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This exception is generated when the _hardware management console_ communicates with a _Processing Unit_ and that the _Processing Unit_ relays the event to an _Execution Engine_.
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Data can be passed alongside the exception and would be stored in main memory by the _Processing Unit_ communications controller.
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IO::
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This exception is generated when an I/O device communicates with the _Execution Engine_.
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Data can be passed alongside the exception and would be stored in main memory by the I/O system.
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== Registers
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=== General Purpose Registers
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General purpose registers (GPRs) are used to perform calculations and store intermediate values. There are 8 GPRs in an Execution Engine. These registers are named *_r0_* through *_r7_*.
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General purpose registers (GPRs) are used to perform calculations and store intermediate values.
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There are 8 GPRs in an Execution Engine. These registers are named *_r0_* through *_r7_*.
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=== Special Purpose Registers
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.Special purpose registers
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[cols="1,1,1,1,3"]
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|===
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|Name |User-mode |Supervisor-mode |Fault-mode |Description
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