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Added info on the hardware debug logging output register in ss3
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Elyan 2024-11-01 16:06:08 +01:00
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src/execution-engine-spec/subsystems.adoc
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@ -40,7 +40,8 @@ The {central-arch-name} allows up to 16 subystem identifiers. Not all of these i
===== sr0: Simulation Control
The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes.
Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *PrivFault* exception if it happens.
Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated.
Real hardware should generate an *PrivFault* exception if it happens.
[source]
----
@ -56,3 +57,43 @@ Writing a value to it while under simulation has the effect of ending the simula
* Writing 0 ends the simulation normaly
* Writing any other value ends the simulation with an error
===== sr1: Hardware Debug Logging Output
The Hardware Debug Logging Output register is 32-bits wide. It is accessible in unprivileged and privileged modes.
The register is write-only and thus reading it in any privilege level generates a *PrivFault* exception.
Writing the address of a NUL-terminated character sequence to this register has the effect of outputting it with a given log level (passed in `cmd`).
A maximum of 80 characters can be outputted at a time if no NUL character is encountered.
[source]
----
ssw ss3, r0, sr1, 0 <1>
ssw ss3, r0, sr1, 8 <2>
----
<1> Writes a NUL-terminated character sequence the address of which is in r0, with a TRACE level.
<2> Writes a NUL-terminated character sequence the address of which is in r0, with an ERROR level.
.Log levels
[cols=""]
|===
|Value |Level
|0
|TRACE
|1
|DEBUG
|2
|INFO
|4
|WARNING
|8
|ERROR
|12
|FATAL
|===