Added info on the hardware debug logging output register in ss3
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@ -40,7 +40,8 @@ The {central-arch-name} allows up to 16 subystem identifiers. Not all of these i
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===== sr0: Simulation Control
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===== sr0: Simulation Control
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The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes.
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The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes.
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Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *PrivFault* exception if it happens.
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Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated.
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Real hardware should generate an *PrivFault* exception if it happens.
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[source]
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[source]
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----
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----
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@ -56,3 +57,43 @@ Writing a value to it while under simulation has the effect of ending the simula
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* Writing 0 ends the simulation normaly
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* Writing 0 ends the simulation normaly
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* Writing any other value ends the simulation with an error
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* Writing any other value ends the simulation with an error
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===== sr1: Hardware Debug Logging Output
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The Hardware Debug Logging Output register is 32-bits wide. It is accessible in unprivileged and privileged modes.
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The register is write-only and thus reading it in any privilege level generates a *PrivFault* exception.
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Writing the address of a NUL-terminated character sequence to this register has the effect of outputting it with a given log level (passed in `cmd`).
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A maximum of 80 characters can be outputted at a time if no NUL character is encountered.
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[source]
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----
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ssw ss3, r0, sr1, 0 <1>
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ssw ss3, r0, sr1, 8 <2>
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----
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<1> Writes a NUL-terminated character sequence the address of which is in r0, with a TRACE level.
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<2> Writes a NUL-terminated character sequence the address of which is in r0, with an ERROR level.
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.Log levels
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[cols=""]
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|===
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|Value |Level
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|0
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|TRACE
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|1
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|DEBUG
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|2
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|INFO
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|4
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|WARNING
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|8
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|ERROR
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|12
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|FATAL
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|===
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