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Added details for subsystem register sr0: Simulation Control
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Elyan 2024-10-31 15:09:49 +01:00
parent 5f44805554
commit 32d34b9283
2 changed files with 8 additions and 5 deletions
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9
src/execution-engine-spec/subsystems.adoc
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@ -40,7 +40,7 @@ The {central-arch-name} allows up to 16 subystem identifiers. Not all of these i
===== sr0: Simulation Control
The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes.
Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *UnknownInstr* exception if it happens.
Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *PrivFault* exception if it happens.
[source]
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@ -50,6 +50,9 @@ ssw ss3, r0, sr0, 0 <2>
<1> Read the Simulation Control register.
<2> Write in the Simulation Control register.
The register contains the value 1 when under simulation and 0 otherwise.
Writing any value to it while under simulation has the effect of ending the simulation.
The register contains the value 1 if under simulation and 0 otherwise. +
Writing a value to it while under simulation has the effect of ending the simulation:
* Writing 0 ends the simulation normaly
* Writing any other value ends the simulation with an error

4
src/execution-engine-spec/system-behavior.adoc
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@ -18,11 +18,11 @@ The _Execution Engine_ starts execution in Supervisor mode.
|N/A
|pc_user, pc_fault
|0x0000_0004
|0x0000_0000
|#TODO: Describe it#
|pc_svc
|0x0000_0000
|0x0000_0004
|#TODO: Describe it#
|psr