Added details for subsystem register sr0: Simulation Control
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@ -40,7 +40,7 @@ The {central-arch-name} allows up to 16 subystem identifiers. Not all of these i
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===== sr0: Simulation Control
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===== sr0: Simulation Control
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The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes.
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The Simulation Control register is a register that is 32-bits wide. It is accessible in unprivileged and privileged modes.
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Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *UnknownInstr* exception if it happens.
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Writing to it is only possible when the _Execution Engine_ in which the software executes is being simulated. Real hardware should generate an *PrivFault* exception if it happens.
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[source]
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[source]
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----
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----
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@ -50,6 +50,9 @@ ssw ss3, r0, sr0, 0 <2>
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<1> Read the Simulation Control register.
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<1> Read the Simulation Control register.
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<2> Write in the Simulation Control register.
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<2> Write in the Simulation Control register.
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The register contains the value 1 when under simulation and 0 otherwise.
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The register contains the value 1 if under simulation and 0 otherwise. +
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Writing any value to it while under simulation has the effect of ending the simulation.
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Writing a value to it while under simulation has the effect of ending the simulation:
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* Writing 0 ends the simulation normaly
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* Writing any other value ends the simulation with an error
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@ -18,11 +18,11 @@ The _Execution Engine_ starts execution in Supervisor mode.
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|N/A
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|N/A
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|pc_user, pc_fault
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|pc_user, pc_fault
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|0x0000_0004
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|0x0000_0000
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|#TODO: Describe it#
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|#TODO: Describe it#
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|pc_svc
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|pc_svc
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|0x0000_0000
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|0x0000_0004
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|#TODO: Describe it#
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|#TODO: Describe it#
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|psr
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|psr
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