Added the other LDR variants and the SVC instruction, updated layout

src/execution-engine-spec/instructions.adoc

@@ -33,6 +33,7 @@ sre::
 cmd::
     Subsystem command.
 
+<<<
 === Instruction list
 #TODO: List instructions#
 
@@ -46,7 +47,8 @@ cmd::
 * system mode instructions (svc, uret, sret, ...)
 * subsystems instructions (ssr & ssw)
 
-==== The NOP instruction
+==== Miscellaneous instructions
+===== NOP: No Operation
 [wavedrom, ,svg]
 ....
 {reg: [
@@ -59,6 +61,7 @@ Description::
     Does nothing. Can be used to align a block of instructions.
 Encoding:: D2-Type
 Assembler syntax::
++
 [source]
 ----
 nop
@@ -67,6 +70,47 @@ Privileged instruction:: No.
 Updates program state flags:: No.
 Exceptions:: None.
 
+<<<
+===== SVC: Supervisor Call
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 0x7f, type: 8, attr: '0x7f'},
+  {bits: 25, name: 'svc_num', type: 5}
+], config: {label: {right: 'SVC'}}}
+....
+
+Description::
+    Generates an SVC exception to execute a privileged operation.
+Encoding:: D2-Type
+Assembler syntax::
++
+[source]
+----
+svc <svc_num>
+----
++
+Where:
+[horizontal]
+svc_num:::
+    A constant identifying the privileged operation to execute. +
+    Must be in the range 0-33554431 (0x0-0x1FFFFFF).
+
+Examples::
++
+[source]
+----
+svc 128  <1>
+svc 0xff <2>
+----
+<1> Calls the privileged operation number 128 that is exposed by the kernel.
+<2> Calls the privileged operation number 255 that is exposed by the kernel.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions:: SVC.
+
+<<<
 ==== Memory-related instructions
 ===== LDR: Load Register
 [wavedrom, ,svg]
@@ -138,7 +182,32 @@ Exceptions:: None.
 ], config: {label: {right: 'LDROW'}}}
 ....
 
-====== LDRIR: Load Register Immediate Pre-indexed
+[frame=ends,grid=rows,cols="1,1"]
+|===
+|Instruction variant | Description
+
+|LDRIR
+|<<LDRIR>>
+
+|LDRIRW
+|<<LDRIRW>>
+
+|LDRIOW
+|<<LDRIOW>>
+
+|LDRR
+|<<LDRR>>
+
+|LDRRW
+|<<LDRRW>>
+
+|LDROW
+|<<LDROW>>
+|===
+
+<<<
+[id=LDRIR]
+====== LDRIR: Load Register+Immediate Pre-indexed
 Description::
     Loads a word from memory into a register.
     The immediate offset `off` is added to the address in the `src` register before reading memory.
@@ -164,23 +233,22 @@ Examples::
 +
 [source]
 ----
-ldr    r1, [r0]    ; Reads a word from the memory address in r0 into r1.
+ldr    r1, [r0]    <1>
-ldr    r3, [r2, 8] ; Reads a word from the memory address in r2, with a 8 bytes
+ldr    r3, [r2, 8] <2>
-                   ; offset, into r3.
+ldr.eq r5, [r4]    <3>
-ldr.eq r5, [r4]    ; If the last comparison resulted in an 'eq' condition status,
-                   ; then reads a word from the memory address in r4 into r5.
-                   ; Else, does nothing.
 ----
+<1> Reads a word from the memory address in r0 into r1.
+<2> Reads a word from the memory address in r2, with an 8 bytes offset, into r3.
+<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5. Else, does nothing.
 
 Privileged instruction:: No.
 Updates program state flags:: No.
 Exceptions::
-[horizontal]
+    MemFault.
-    MemFault:::
-        If the memory address being accessed is invalid, non readable or not paged in.
-        The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place.
 
-====== LDRIRW: Load Register Immediate Pre-indexed with Write-back
+<<<
+[id=LDRIRW]
+====== LDRIRW: Load Register+Immediate Pre-indexed with Write-back
 Description::
     Increments the source register then reads a word from memory into the destination register.
     The immediate offset `off` is added to the `src` register value before reading a word from memory into the `dst` register.
@@ -206,20 +274,165 @@ Examples::
 +
 [source]
 ----
-ldr    r1, ![r0]    ; Increments r0 by 4 then reads a word from the memory address
+ldr    r1, ![r0]    <1>
-                    ; in r0 into r1.
+ldr    r3, ![r2, 8] <2>
-ldr    r3, ![r2, 8] ; Increments r2 by 8 then reads a word from the memory address
+ldr.eq r5, ![r4]    <3>
-                    ; in r2 into r3.
-ldr.eq r5, ![r4]    ; If the last comparison resulted in an 'eq' condition status,
-                    ; then increments r4 by 4 and reads a word from the memory
-                    ; address in r4 into r5. Else, does nothing.
 ----
+<1> Increments r0 by 4 then reads a word from the memory address in r0 into r1.
+<2> Increments r2 by 8 then reads a word from the memory address in r2 into r3.
+<3> If the last comparison resulted in an 'eq' condition status, increments r4 by 4 then reads a word from the memory address in r4 into r5. Else, does nothing.
 
 Privileged instruction:: No.
 Updates program state flags:: No.
 Exceptions::
-[horizontal]
+    MemFault.
-    MemFault:::
+
-        If the memory address being accessed is invalid, non readable or not paged in.
+<<<
-        The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place.
+[id=LDRIOW]
+====== LDRIOW: Load Register+Immediate Post-indexed with Write-back
+Description::
+    Reads a word from memory into the destination register then increments the source register.
+    The immediate offset `off` is added to the source register `src` after reading from memory into the destination register `dst`.
+Encoding:: A-Type
+Assembler syntax::
++
+[source]
+----
+ldr<cond?> <dst>, [<src>, <off?>]!
+----
++
+Where:
+[horizontal]
+cond::: Optional condition.
+dst::: Destination register.
+src::: Source register.
+off:::
+    Optional offset immediate.
+    Must be a multiple of 4 and in the range 0-8188.
+    If omitted, then 4 is used.
+
+Examples::
++
+[source]
+----
+ldr    r1, [r0]!    <1>
+ldr    r3, [r2, 8]! <2>
+ldr.eq r5, [r4]!    <3>
+----
+<1> Reads a word from the memory address in r0 into r1 then increments r0 by 4.
+<2> Reads a word from the memory address in r2 into r3 then increments r2 by 8.
+<3> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r4 into r5 then increments r4 by 4. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
+
+<<<
+[id=LDRR]
+====== LDRR: Load Register+Register Pre-indexed
+Description::
+    Loads a word from memory into a register.
+    The value in the register `off` is added to the address in the `src` register before reading memory.
+Encoding:: A-Type
+Assembler syntax::
++
+[source]
+----
+ldr<cond?> <dst>, [<src>, <off>]
+----
++
+Where:
+[horizontal]
+cond::: Optional condition.
+dst::: Destination register.
+src::: Source register.
+off::: Offset register.
+
+Examples::
++
+[source]
+----
+ldr    r1, [sp, r0] <1>
+ldr.eq r0, [r1, r2] <2>
+----
+<1> Reads a word from the memory address in sp into r1, adding the value of r0 as an offset.
+<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0, adding the value of r2 as an offset. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
+
+<<<
+[id=LDRRW]
+====== LDRRW: Load Register+Register Pre-indexed with Write-back
+Description::
+    Increments the source register then reads a word from memory into the destination register.
+    The value in the register `off` is added to the `src` register value before reading a word from memory into the `dst` register.
+Encoding:: A-Type
+Assembler syntax::
++
+[source]
+----
+ldr<cond?> <dst>, ![<src>, <off>]
+----
++
+Where:
+[horizontal]
+cond::: Optional condition.
+dst::: Destination register.
+src::: Source register.
+off::: Offset register.
+
+Examples::
++
+[source]
+----
+ldr    r1, ![sp, r0] <1>
+ldr.eq r0, ![r1, r2] <2>
+----
+<1> Adds the value of r0 into sp then reads a word from the memory address in sp into r1.
+<2> If the last comparison resulted in an 'eq' condition status, adds the value of r2 into r1 then reads a word from the memory address in r1 into r0. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
+
+<<<
+[id=LDROW]
+====== LDROW: Load Register+Register Post-indexed with Write-back
+Description::
+    Reads a word from memory into the destination register then increments the source register.
+    The value in the register `off` is added to the source register `src` after reading from memory into the destination register `dst`.
+Encoding:: A-Type
+Assembler syntax::
++
+[source]
+----
+ldr<cond?> <dst>, [<src>, <off>]!
+----
++
+Where:
+[horizontal]
+cond::: Optional condition.
+dst::: Destination register.
+src::: Source register.
+off::: Offset register.
+
+Examples::
++
+[source]
+----
+ldr    r1, [sp, r0]! <1>
+ldr.eq r0, [r1, r2]! <2>
+----
+<1> Reads a word from the memory address in sp into r1 then adds the value of r0 into sp.
+<2> If the last comparison resulted in an 'eq' condition status, reads a word from the memory address in r1 into r0 then adds the value of r2 into r1. Else, does nothing.
+
+Privileged instruction:: No.
+Updates program state flags:: No.
+Exceptions::
+    MemFault.
 

src/execution-engine-spec/intro.adoc

@@ -70,8 +70,9 @@ SVC::
     Supervisor calls are used to perform privileged actions in a secure manner as the kernel consistently performs security checks whenever it processes requests from user-mode software.
 
 MemFault::
-    A memory fault is generated when an instruction references a memory address that is not mapped in virtual memory or is invalid (e.g. does not exist virtually and physically).
+    A memory fault is generated when an instruction references a memory address that is invalid, non readable or not paged in.
     This exception can be generated when attempting to read or write memory as well as when attempting to fetch an instruction.
+    The kernel may update the page table entries and re-execute the instruction without the user application being aware that it failed in the first place.
 
 SysTick::
     This exception is generated each time a system programed timer ticks at regular intervals.